參數(shù)資料
型號: SAF-XC2220U-8F66V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQCC48
封裝: 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁數(shù): 91/106頁
文件大?。?/td> 3017K
代理商: SAF-XC2220U-8F66V
XC2220U
XC2000 Family / Compact Line
Electrical Parameters
PRELIMINARY
Data Sheet
81
V1.0, 2010-12
4.6.3
External Clock Input Parameters
These parameters specify the external clock generation for the XC2220U. The clock can
be generated in two ways:
By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
By supplying an external clock signal. This clock signal can be supplied either to
pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).
If connected to CLKIN1, the input signal must reach the defined input levels
V
IL and VIH.
If connected to XTAL1, a minimum amplitude
V
AX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (
t
1 … t4) are only valid for an external clock
input signal.
Note: Operating Conditions apply.
Table 27
External Clock Input Characteristics
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Oscillator frequency
f
OSC SR
4
40
MHz Input= Clock
Signal
4
16
MHz Input= Crystal
or Resonator
XTAL1 input current
absolute value
|
I
IL| CC
20
μA
Input clock high time
t
1 SR
6
ns
Input clock low time
t
2 SR
6
ns
Input clock rise time
t
3 SR
88
ns
Input clock fall time
t
4 SR
88
ns
Input voltage amplitude on
XTAL11)
1) The amplitude voltage
VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by
VIX1.
V
AX1 SR
0.3 x
V
DDIM
V
f
OSC<16MHz;
f
OSC≥ 4MHz
0.4 x
V
DDIM
V
f
OSC≥ 16 MHz;
f
OSC≤ 20 MHz
0.5 x
V
DDIM
V
f
OSC>20MHz;
f
OSC≤ 40 MHz
Input voltage range limits
for signal on XTAL1
V
IX1 SR
-1.7 +
V
DDIM
1.7
V
2)
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