參數(shù)資料
型號: SAF-XC164S-16F40F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機與C166SV2核心
文件頁數(shù): 23/72頁
文件大?。?/td> 763K
代理商: SAF-XC164S-16F40F
XC164S
Derivatives
Functional Description
Data Sheet
19
V1.0, 2005-01
3.3
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Central Processing Unit (CPU)
Figure 4
CPU Block Diagram
Based on these hardware provisions, most of the XC164S’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. Also multiplication and most MAC
instructions execute in one single cycle. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: for example, a 32-/16-bit
division is started within 4 cycles, while the remaining 15 cycles are executed in the
a
d
d
CSP
IP
CPUCON1
CPUCON2
CPUID
FIFO
IFU
IDX0
IDX1
QX0
QX1
QR1
QR0
SP
SPSEG
VECSEG
TFR
STKOV
STKUN
DPP0
DPP1
DPP2
DPP3
+/-
+/-
ADU
MDL
Ones
MDH
Zeros
MAL
Division Unit
Multiply Unit
MAH
Multiply Unit
MSW
MCW
ALU
RF
+/-
+/-
PSW
MRW
MDC
Barrel-Shifter
Bit-Mask-Gen.
WB
MAC
CPU
Buffer
CP
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
IPIP
DPRAM
a
data in
data out
DMU
R14
R0
R1
GPRs
R15
RR15
R0
R1
R15
R14
R0
R1
GGPRs
R15
R14
R0
R1
GPRs
SRAM
d
address
d
Peripheral-Bus
PMU
Internal Program Memory
System-Bus
a
d
d
System-Bus
Prefetch Unit
Branch Unit
Return Stack
Injection/Exception
Handler
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