參數(shù)資料
型號: SAF-C161K-LM HA
廠商: Infineon Technologies
文件頁數(shù): 66/66頁
文件大?。?/td> 0K
描述: IC MCU 16BIT ROM/LESS MQFP-80-1
標(biāo)準(zhǔn)包裝: 504
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 20MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 63
程序存儲器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-QFP
包裝: 托盤
其它名稱: C161KLMHAFAQMA1
C161KLMHAFXQMA1
F161KLMHAXP
SAF-C161K-LMHA
SAF-C161K-LMHA-ND
SAF-C161K-LMHAIN
SAFC161KLMHAX
SP000011620
C161K
C161O
Data Sheet
5
V2.0, 2001-01
Table 2
Pin Definitions and Functions
Symbol Pin
Num
Input
Outp.
Function
XTAL1
XTAL2
2
3
I
O
XTAL1:
Input to the oscillator amplifier and input
to the internal clock generator
XTAL2:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
P3
IO
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The Port 3 pins serve for following
alternate functions:
P3.2
5
I
CAPIN
GPT2 Register CAPREL Capture Input
This alternate input is only available in the C161O.
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
6
7
8
9
10
11
12
13
14
15
16
O
I
I/O
O
I/O
O
I/O
T3OUT
GPT1 Timer T3 Toggle Latch Output
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
MRST
SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR
SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0
ASC0 Clock/Data Output (Async./Sync.)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
External Memory High Byte Enable Signal,
WRH
External Memory High Byte Write Strobe
SCLK
SSC Master Clock Output / Slave Clock Input
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
17
18
19
20
23
24
IO
O
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 4 can be used to output the segment
address lines:
A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Most Significant Segment Address Line
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