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參數(shù)資料
| 型號： | SAB83C517A-N18-T4 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 18 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 47/137頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | SAB83C517A-N18-T4 |
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Semiconductor Group
3 - 9
Memory Organization
3.4
Architecture for the XRAM
The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the
contents is undefined, while it remains unchanged during and after a reset or HW Power Down if
the power supply is not turned off.
The additional On-Chip RAM is logically located in the "external data memory" range at the upper
end of the 64 KByte address range (F800H-FFFFH). It is possible to enable and disable (only by
reset) the XRAM. If it is disabled the device shows the same behaviour as the parts without XRAM,
i.e. all MOVX accesses use the external bus to physically external data memory.
3.4.1 Accesses to XRAM
Because the XRAM is used in the same way as external data memory the same instruction types
must be used for accessing the XRAM.
Note:
If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the cycle which
the reset is detected at (MOVX is a 2-cycle instruction):
Reset detection at cycle 1: The new value will not be written to XRAM. The old value is not
affected.
Reset detection at cycle 2: The old value in XRAM is overwritten by the new value.
Accesses to XRAM using the DPTR
There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR for
indirect addressing. The instructions are:
MOVX
A, @DPTR
(Read)
MOVX
@DPTR, A
(Write)
Normally the use of these instructions would use a physically external memory. However, in the
SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address
space (DPTR
≥ F800H).
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