- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374693 > SAB80C515A-M18-T3 (SIEMENS A G) 8-Bit CMOS Single-Chip Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | SAB80C515A-M18-T3 |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 18 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 16/57頁 |
| 文件大小： | 899K |
| 代理商： | SAB80C515A-M18-T3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
SAB 80C515A/83C515A-5
Semiconductor Group
15
Accesses to XRAM
Because the XRAM is used in the same way as external data memory the same instruction
types must be used for accessing the XRAM.
Note:
If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the
cycle which the reset is detected at (MOVX is a 2-cycle instruction):
Reset detection at cycle 1:
The new value will not be written to XRAM. The old value
is not affected.
Reset detection at cycle 2:
The old value in XRAM is overwritten by the new value.
Accesses to XRAM using the DPTR
There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR
for indirect addressing. The instructions are:
MOVX A,
@DPTR (Read)
MOVX
@DPTR, A (Write)
Normally the use of these instructions would use a physically external memory. However, in the
SAB 80C515A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM
address space (DPTR
≥
F800
H
).
Accesses to XRAM using the Registers R0/R1
The 8051 architecture provides also instructions for accesses to external data memory range
which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions
are:
MOVX A,
@Ri (Read)
MOVX
@Ri, A (Write)
In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as
page register which selects pages of 256-byte. However, the distinction, whether Port 2 is
used as general purpose I/O or as "page address" is made by the external system design. From
the device’s point of view it cannot be decided whether the Port 2 data is used externally as
address or as I/O data!
Hence, a special page register is implemented into the SAB 80C515A to provide the possibility
of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same
function for the XRAM as Port 2 for external data memory.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAB83C515A-5M18-T3 | 8-Bit CMOS Single-Chip Microcontroller |
| SAB83C515A-5N18 | |
| SAB83C515A-5N18-T3 | 8-Bit CMOS Single-Chip Microcontroller |
| SAB83C515A-5 | 8-Bit CMOS Single-Chip Microcontroller |
| SAB80C515A-N18 | 8-Bit CMOS Single-Chip Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAB80C515AN18 | 制造商:Infineon Technologies AG 功能描述:MCU 8-Bit C500 8051 CISC ROMLess 5V 68-Pin PLCC |
| SAB-80C515A-N18 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| SAB80C515A-N18 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB80C515A-N18-T3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Single-Chip Microcontroller |
| SAB80C515AN18T4TR | 制造商:Infineon Technologies AG 功能描述:MCU 8-bit C500 8051 CISC ROMLess 5V 68-Pin PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。