參數(shù)資料
型號: SAB80C166W
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
封裝: EIAJ, PLASTIC, MQFP-100
文件頁數(shù): 45/67頁
文件大?。?/td> 878K
代理商: SAB80C166W
SAB 80C166W/83C166W
Semiconductor Group
5
29
NMI
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI pin
must be low in order to force the SAB 80C166W/83C166W to
go into power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pull NMI high externally.
29
ALE
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
26
RD
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
30 - 37
40 - 47
P1.0 –
P1.15
I/O
Port 1 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode..
48 - 53
56 - 59
P5.0 –
P5.9
I
Port 5 is a 10-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 10)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x).
62 - 77
62
75
76
77
P2.0 –
P2.15
I/O
O
I/O
O
I/O
I
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 2 pins also serve for alternate functions:
P2.0
CC0IO
CAPCOM: CC0 Cap.-In/Comp.Out
...
P2.13
CC13IO
CAPCOM: CC13 Cap.-In/Comp.Out,
BREQ
External Bus Request Output
P2.14
CC14IO
CAPCOM: CC14 Cap.-In/Comp.Out,
HLDA
External Bus Hold Acknowl. Output
P2.15
CC15IO
CAPCOM: CC15 Cap.-In/Comp.Out,
HOLD
External Bus Hold Request Input
Pin Definitions and Functions (cont’d)
Pin
No.
Symbol
Input (I)
Output (O)
Function
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