參數(shù)資料
型號(hào): SAB-C517A-4RM
廠商: SIEMENS A G
元件分類(lèi): 微控制器/微處理器
英文描述: 8-Bit CMOS Microcontroller
中文描述: 8-BIT, MROM, 18 MHz, MICROCONTROLLER, PQFP100
文件頁(yè)數(shù): 30/67頁(yè)
文件大小: 479K
代理商: SAB-C517A-4RM
C517A
Semiconductor Group
30
1997-10-01
The main functional blocks of the CCU are:
– Timer 2 with
f
OSC
/12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and
overflow interrupt request.
– Compare timer with
f
OSC
/2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt
request.
– Compare/(reload/) capture register array consisting of four different kinds of registers:
one 16-bit compare/reload/capture register,
three 16-bit compare/capture registers,
one 16-bit compare/capture register with additional “concurrent compare” feature,
eight 16-bit compare registers with timer-overflow controlled loading.
Table 6
shows the possible configurations of the CCU and the corresponding compare modes
which can be selected. The following sections describe the function of these configurations.
Table 6
CCU Configurations
Assigned
Timer
Compare
Register
Compare Output at
Possible Modes
Timer 2
CRCH/CRCL
CCH1/CCL1
CCH2/CCL2
CCH3/CCL3
CCH4/CCL4
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2/CC4
Compare mode 0, 1 + Reload
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
Compare mode 0, 1 / capture
CCH4/CCL4
P1.4/INT2/CC4
P5.0/CCM0
to
P5.7/CCM7
Compare mode 1
“Concurrent compare“
CMH0/CML0
to
CMH7/CML7
P4.0/CM0
to
P4.7/CM7
Compare mode 0
COMSET
COMCLR
P5.0/CCM0
to
P5.7/CCM7
Compare mode 2
Compare
Timer
CMH0/CML0
to
CMH7/CML7
P4.0/CM0
to
P4.7/CM7
Compare mode 1
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