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參數(shù)資料
| 型號： | SAB-C513AO |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 33/59頁 |
| 文件大小： | 1634K |
| 代理商： | SAB-C513AO |
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C513AO
Data Sheet
31
02.00
Fail Save Mechanisms
The C513AO offers enhanced fail-safe mechanisms which allow automatic recovery from a
software upset or a hardware failure:
A programmable Watchdog Timer (WDT) has variable time-out period from 512
μ
s up to approx.
1.1 sec. at 12 MHz
An Oscillator Watchdog (OWD) monitors the on-chip oscillator and forces the microcontroller into
reset state if the on-chip oscillator fails. It also provides the clock for a fast internal reset after
power-on.
The Watchdog Timer in the C513AO is a 15-bit timer which is incremented by a count rate of either
f
CYCLE
/2 or
f
CYCLE
/32 (
f
CYCLE
=
f
OSC
/12). That is, the machine clock is divided by a fixed divide-by-two
prescaler and an optional divide-by-16 prescaler arranged in series. For programming of the
watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written.
Figure 17
shows
the block diagram of the watchdog timer unit.
Figure 17
Block Diagram of the Watchdog Timer
The Watchdog Timer can be started by software (bit SWDT in SFR WDCON); but, it cannot be
stopped during active mode of the device. If the software fails to clear the Watchdog Timer, an
internal reset will be initiated. The reset cause can be examined by software (status flag WDTS in
WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR WDCON) and
SWDT consecutively. This double instruction sequence has been implemented to increase system
security. During a refresh, the content of the SFR WDTREL is transferred to SFR WDTH, i.e. the
upper 7-bit of the watchdog timer. It must be noted, however, that the watchdog timer is stopped
during the idle mode and power down mode of the processor.
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