參數(shù)資料
型號(hào)： SAA7740H
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Audio Processing IC DAPIC
中文描述： 4-BIT, 23 MHz, OTHER DSP, PQFP64
封裝： 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, QFP-64
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 142K
代理商： SAA7740H
1997 May 30
20
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
I
2
S-BUS PROTOCOL
The I
2
S-bus digital interface is used for communication to
external digital sources. It is a 3-line serial bus with one
line each for data, clock and word select. Figure 11
illustrates an excerpt from the Philips I
2
S-bus specification
interface report with respect to general timing and format
of the bus. Word select (WS) at logic 0 signifies the left
channel and logic 1 the right channel.
The serial data is transmitted in two’s complement with
MSB first. One clock period after the negative edge of the
WS line, the MSB of the left channel is transmitted. Data is
synchronized on the negative edge of the clock and
latched on the positive edge.
Two data line have been implemented as input from an
external processor for the four audio channels. Because of
this configuration the DAPIC operates in the following
manner.
The I
2
S-bus input block reads 4 samples (left and right
samples of the front and rear channel) and stores the
information into the register file. The operators read from
the register file, process the data and store the
intermediate results back into the register file. If a delay
line is required, the external RAM will need to be
accessed. The output samples are read from the register
file and are passed via the fade unit to the I
2
S-bus output
block. The same operation is repeated for each incoming
audio sample.
Fig.11 I
2
S-bus timing format.
handbook, full pagewidth
MLC159
SCK
SD
SCK
WS
MSB
LEFT
MSB
RIGHT
SD
WS
tHC
tLC
T
thr
tsr
VIH
VIL
VIH
VIL
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