參數(shù)資料
型號(hào)： SAA7712H
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)字信號(hào)處理
英文描述： Sound effects DSP(聲音效應(yīng)數(shù)字信號(hào)處理器)
中文描述： 0-BIT, 32.544 MHz, OTHER DSP, PQFP80
文件頁(yè)數(shù)： 23/44頁(yè)
文件大?。?/td> 178K
代理商： SAA7712H
1999 Aug 05
23
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.6.6
A
CKNOWLEDGE
The number of data bits transferred between the START
and STOP conditions from the transmitter to the receiver
is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.13). The acknowledge bit is a
HIGH-level left on the bus by the transmitter whereas the
master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line (left HIGH by the transmitter) during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse.
Set-up and hold times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Fig.14).
8.6.7
S
TATE OF THE
I
2
C-
BUS INTERFACE DURING AND
AFTER
P
OWER
-
ON RESET
Duringreset(seeSection 8.8),theinternalSDAlineiskept
HIGH and pin SDA is therefore high-impedance. The SDA
line remains HIGH until a master pulls it down to initiate
communication.
Fig.14 Acknowledge on the I
2
C-bus.
handbook, full pagewidth
MGS219
S
START condition
1
2
7
8
9
data output
by receiver
SCL from
master
clock pulse for
acknowledgement
data output
by transmitter
acknowledge
not acknowledge
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