參數(shù)資料
型號(hào): SAA7377
廠商: NXP Semiconductors N.V.
英文描述: Digital servo processor and Compact Disc decoder CD7
中文描述: 數(shù)字伺服處理器和CD7抗原光盤解碼器
文件頁(yè)數(shù): 18/56頁(yè)
文件大?。?/td> 311K
代理商: SAA7377
1998 Jul 06
18
Philips Semiconductors
Product specifications
Digital servo processor and Compact Disc
decoder (CD7)
SAA7377
7.10
KILL circuit
The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left or right channel
before the digital filter. The output is switched active LOW
when silence has been detected for at least 250 ms, or if
mute is active. Two modes are available which can be
selected by register C:
1 pin kill: KILL active LOW indicates silence detected on
both left and right channels.
2 pin kill: KILL active LOW indicates silence detected on
left channel. V3 active LOW indicates silence detected
on right channel.
7.11
The VIA interface
The SAA7377 has five pins that can be reconfigured for
different applications (see Table 8).
Table 8
Pin applications
PIN NAME
PIN
NUMBER
TYPE
CONTROL
REGISTER
ADDRESS
CONTROL
REGISTER
DATA
FUNCTION
V1
62
input
1100
xxx1
xxx0
external off-track signal input
internal off-track signal used, input may be read
via decoder status bit; selected via register 2
input may be read via decoder status bit;
selected via register 2
KILL output for right channel
output = 0
output = 1
4-line motor drive (using V4 and V5)
Q-to-W subcode output
output = 0
output = 1
de-emphasis output (active HIGH)
output = 0
output = 1
V2
63
input
V3
42
output
1100
1101
1101
xx0x
x01x
x11x
0000
xx01
xx10
xx11
01xx
10xx
11xx
V4
41
output
V5
40
output
7.12
Spindle motor control
7.12.1
M
OTOR OUTPUT MODES
The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±
8 frame FIFO and disc speed information are used to
calculate the motor control output signals. Several output
modes, selected by register 6, are supported:
Pulse density, 2-line (true complement output), 1 MHz
sample frequency
PWM output, 2-line, 22.05 kHz modulation frequency
PWM output, 4-line, 22.05 kHz modulation frequency
CDV motor mode.
7.12.1.1
Pulse density output mode
In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal. A 50%
duty factor corresponds with the motor not actuated,
higher duty factors mean acceleration, lower mean
braking. In this mode, the MOTO2 signal is the inverse of
the MOTO1 signal. Both signals change state only on the
edges of a 1 MHz internal clock signal. Possible
application diagrams are illustrated in Fig.13.
7.12.1.2
PWM output mode (2-line)
In the PWM mode the motor acceleration signal is put
in pulse-width modulation form on the MOTO1 output.
The motor braking signal is pulse-width modulated on the
MOTO2 output. The timing is illustrated in Fig.14. A typical
application diagram is illustrated in Fig.15.
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