參數(shù)資料
型號(hào): SAA7373
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Digital servo processor and Compact Disc decoder CD7
中文描述: 數(shù)字伺服處理器和CD7抗原光盤(pán)解碼器
文件頁(yè)數(shù): 16/60頁(yè)
文件大?。?/td> 323K
代理商: SAA7373
1998 Jul 06
16
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
SAA7373
7.8
DAC interface
The SAA7373 is compatible with a wide range of digital-to-analog converters (DACs). Eleven formats are supported and
are given in Table 4. Figures 11 and 12 show the Philips I
2
S-bus and the EIAJ data formats respectively. When the
decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor ‘d’. All formats are
MSB first and f
s
is (44.1
×
n) kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7. It
should be noted that EF is only a defined output in CD ROM and 1f
s
modes.
Table 4
DAC interface formats
Note
1.
In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated
then the first 18 bits contain data.
REGISTER 3
SAMPLE
FREQUENCY
NUMBER OF
BITS
SCLK (MHz)
FORMAT
INTERPOLATION
1010
1011
1110
0010
0110
0000
0100
1100
0011
0111
1111
f
s
f
s
f
s
f
s
f
s
4f
s
4f
s
4f
s
2f
s
2f
s
2f
s
16
16
2.1168
×
n
2.1168
×
n
2.1168
×
n
2.1168
×
n
2.1168
×
n
8.4672
×
n
8.4672
×
n
8.4672
×
n
4.2336
×
n
4.2336
×
n
4.2336
×
n
CD ROM (I
2
S-bus)
CD ROM (EIAJ)
Philips I
2
S-bus; 16/18 bits
(1)
EIAJ 16 bits
EIAJ 18 bits
EIAJ 16 bits
EIAJ 18 bits
Philips I
2
S-bus; 18 bits
EIAJ 16 bits
EIAJ 18 bits
Philips I
2
S-bus; 18 bits
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
16/18
(1)
16
18
16
18
18
16
18
18
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