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參數(shù)資料
| 型號： | SAA7367 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | Bitstream conversion ADC for digital audio systems |
| 中文描述： | 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 113K |
| 代理商： | SAA7367 |
1998 Nov 17
6
Philips Semiconductors
Product specification
Bitstream conversion ADC for
digital audio systems
SAA7367
Input buffer
Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs), for left and right channels
respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC.
Typically, the operational amplifiers are configured as
low-pass filters with a gain of 1 and a pole at
approximately 5f
s
.
Remark:
the complete ADC is non-inverting. Hence, a
positive DC input (referenced to V
ref
) will yield a positive
digital output.
Input level
The overall system gain is proportional V
DDA
, or more
accurately the potential difference between the DAC
reference voltages (V
VDACP
) and (V
VDACN
). For
convenience, the ADC input signal amplitude is defined as
that amplitude seen on BOL or BOR, the operational
amplifier outputs (i.e. the input to the SDM). Also, the 0 dB
input level is defined as that which gives a
1 dB (actually
1.12 dB) digital output, relative to full-scale swing. This
reduced gain provides headroom to accommodate small
random DC offsets, without causing the digital output to
clip.
Hence:
The user of the IC should ensure that, when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level.
In the event that the maximum signal level cannot be
pre-determined, e.g. live microphone input, the average
signal level should be set at
10 to
20 dB down. The
exact value will depend on the application and the balance
between headroom and operating Signal-to-Noise Ratio
(SNR).
Behaviour during overload
As previously defined, the maximum input level for normal
operation is 0 dB. If the input level exceeds this value,
clipping may occur. Within the system, excessive
amplitudes are detected after the high-pass filter.
Infringements are limited to the maximum permitted
positive or negative values 2
17
1 or
2
17
respectively.
V
I
0 dB
(
)
V
5 V (RMS)
VDACN
-------------------------------V
)
=
Input signals in the range 0 to 1 dB may or may not be
clipped, depending on the values of DC dither and small
random offsets in the analog circuitry.
When using the recommended application circuitry,
clipping will initially be observed on negative peaks, due to
the use of negative DC dither.
The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the
recommended circuit, the following applies: the inverting
operational amplifier inputs BIL and BIR are protected
from excessive voltages (currents) by diodes to V
DDA
and
V
SSA
. These have absolute maximum ratings of
I
d
=
±
20 mA, with a safe practical limit of
±
2 mA.
Given the input resistor of 10 k
,
±
2 mA diode current and
the operation of the operational amplifier, a maximum
signal (applied to the input resistor) of
±
30 V can be
handled safely. This level represents an overload of 26 dB.
During overload, the in-band portion of the waveform will
be correctly converted. The out-of-band portion will be
limited as previously detailed.
Sigma-Delta Modulator (SDM)
The SAA7367 uses two third-order SDMs with a
quantization noise floor of approximately
104 dB. The
scaling of the feedback has been optimized for stable
operation, even during overload. Thus, with a maximum
signal swing of 0 V to V
DDA
on the input, the digital output
remains well-behaved, i.e. it does not burst into random
oscillation. During overload, the output is simply a clipped
version of the input. The gain of this stage is
4.64 dB.
Decimation filter
Decimation from 128f
s
is performed in two stages. The first
stage, a comb filter, uses 64 symmetrical coefficients to
implement a 3rd sin
x
x
characteristic. This filter decimates
from 128 to 8f
s
. The second stage, an FIR filter, consists of
three half-band filters, each decimating by a factor of 2.
The overall characteristics are given in Table 3.
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|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
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| SAA7370 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7370A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7371 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7371GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7372 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
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