
May 1994
4
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
PINNING
SYMBOL
PIN
DESCRIPTION
SFOR
1
Serial interface output format select. Output format is selected as follows: SFOR
HIGH = Format 1; SFOR LOW = Format 2.
Standby mode input (active LOW).
Overload indication output. This pin indicates whether the internal digital signal is within 1 dB
of maximum. In standby mode this output is high impedance.
System clock input.
Supply for the digital section (3.4 to 5.5 V).
Ground supply for the digital section.
Serial interface data output. In standby mode this output is high impedance.
Serial interface word select signal. In master mode this pin outputs the serial interface word
select signal. In slave mode this pin is the word select input to the serial interface. In standby
mode this pin is always an input (high impedance).
Serial interface clock. In master mode this pin outputs the serial interface bit clock. In slave
mode this pin is the input for the external bit clock. In standby mode this output is
high impedance.
Test input 1. This pin should be left open-circuit.
High-pass filter enable input. (HPEN HIGH = enabled). If unconnected this pin defaults HIGH.
Test input 2. This pin should be left open-circuit.
Ground supply for the analog section.
Current reference output node.
1
2
V
DDA
reference generator output for the right channel analog section.
Buffer operational amplifier inverting input for right channel.
Buffer operational amplifier output for right channel.
Negative 1-bit DAC reference voltage input, connected to 0 V.
Positive 1-bit DAC reference voltage input, connected to +5 V.
Buffer operational amplifier output for left channel.
Buffer operational amplifier inverting input for left channel.
1
2
V
DDA
reference generator output for the left channel analog section.
Supply for the analog section.
Serial interface operating output mode master/slave select as follows: HIGH = slave mode;
LOW = master mode. If unconnected the pin will default LOW.
STD
OVLD
2
3
CKIN
V
DDD
V
SSD
SDO
SWS
4
5
6
7
8
SCK
9
TEST1
HPEN
TEST2
V
SSA
I
REF
V
REFR
BIR
BOR
V
DACN
V
DACP
BOL
BIL
V
REFL
V
DDA
SLAVE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24