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參數(shù)資料
| 型號： | SAA7219 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | MPEG2 Transport RISC Processor(MPEG2 傳送RISC處理器) |
| 中文描述： | 的MPEG2傳輸RISC處理器（RISC的處理器的MPEG2傳送） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 87K |
| 代理商： | SAA7219 |
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5
PINNING
Table 1
SQFP208 package: 179 functional pins and 29 power supply pins
SYMBOL
PIN
I/O
BUFFER TYPE
VOLT
(1)
DESCRIPTION
PIO interface (32 pins)
PIO0 to PIO7
PIO8/BOOTIS32
105 to 112
113
I/O
I/O
bidirectional, 3 mA output drive 5 V
bidirectional, 3 mA output drive 5 V
usable as interrupt inputs and/or I/O lines
PIO bit and PIO-strap. At power-on, it indicates the
data bus size of the booting device.
PIO bit and PIO-strap. At power-on, if BOOTIS32 is
LOW, it indicates if the system should reboot from a
16-bit or 8-bit device.
PIO bit and PIO-strap
I/O lines or upper 16-bit data bus. The data bus
width of the booting device is automatically
configured at power-on.
PIO9/BOOTIS16
114
I/O
bidirectional, 3 mA output drive 5 V
PIO10 to PIO15
PIO(31:16)/D(31:16)
116 to 121
2, 4 to 9, 11 to 16,
18 to 20
I/O
I/O
bidirectional, 3 mA output drive 5 V
bidirectional, 6 mA output drive 5 V
Extension bus (58 pins)
D15 to D0
21, 22, 24, 25,
28 to 30, 33 to 36,
38 to 41
63 to 65, 67 to 71,
73 to 77, 81 to 85,
87 to 90
49
48
46
43
44
42
62
47
50 to 56
58
59
I/O
bidirectional, 8 mA output drive 3.3 V
lower 16-bit data bus
A0 to A21
O
8 mA output drive
3.3 V
address bus
RAS0N
RAS1N/DCS1N
LCASN
MLCASN
MUCASN
UCASN
WEN
DCS0N
CS6N to CS0N
OEN
DTACKN
O
O
O
O
O
O
O
O
O
O
I
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
8 mA output drive
TTL input
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
5 V
row access strobe for DRAM and SDRAM Bank 0
row access strobe for DRAM and SDRAM Bank 1
column access strobe lower byte
column access strobe mid lower byte
column access strobe mid upper byte
column access strobe upper byte
write enable
chip select for SDRAM Bank 0
chip select
output enable
Data termination acknowledge. Asserted LOW by
the peripheral when the data bus is valid.
selects the graphics SDRAM memory space of the
SAA7215
CS_SDN
60
O
2 mA output drive
3.3 V
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7219HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 Transport RISC processor |
| SAA7220 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DIGITAL FILTER FOR COMPACT DISC DIGITAL AUDIO SYSTEM |
| SAA7221 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
| SAA7221HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
| SAA7221HS/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
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