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參數(shù)資料
| 型號： | SAA7212 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| 中文描述： | 集成MPEG2解碼器的AVG（綜合的MPEG音頻視頻圖表譯碼器） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 93K |
| 代理商： | SAA7212 |
1998 Sep 07
3
Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
SAA7212
Video output direct connectable to SAA718x encoder
family
Various trick modes under control of external
microcontroller in stand-alone mode:
– Freeze field/frame on I or P pictures; restart on I
picture
– Freeze field on B pictures; restart on the next I or P
picture.
– Scanning and decoding of I or I + P pictures in a IBP
sequence
– Single step mode
– Repeat/skip field for time base correction.
MPEG2 audio features
Decoding of 2 channels, layer I and II MPEG audio.
Support for mono, stereo, intensity stereo and dual
channel mode.
Constant and variable bit rates up to 448 kbit/s
Supported audio sampling frequencies: 48, 44.1, 32, 24,
22.05 and 16 kHz
CRC error detection
3 decoding modes for dual channel streams: decoding
of CH1 only, decoding of CH2 only and decoding of both
CH1 and CH2
Storage of last 54 bytes in ancillary data field
Dynamic Range Control (DRC) at output
Independent channel volume control and programmable
inter channel crosstalk through a baseband audio
processing unit
Muting possibility via external controller. Automatic
muting in case of errors or data lack.
Generation of ‘beeps’ with programmable tone height,
duration and amplitude
Serial two channel digital audio output with 16, 18, 20 or
22 bits per sample, compatible either to I
2
S or Japanese
formats. Output can be set to high-impedance mode via
the external controller.
Serial SPDIF audio output. Output can be set to
high-impedance mode.
Clock output 256 or 384
×
f
s
for external DA converter.
Output can be set to high-impedance mode.
Audio FIFO in external SDRAM. Programmable buffer
size, at least 64 kbit is available.
Synchronization modes: PTS controlled, PTS free
running, software controlled, buffer controlled
PTS register can be set via external controller
Programmable processing delay compensation
Software controlled stop and restart functions.
Graphics features
Graphics are presented in boxes independent of video
format
Screen arrangement of boxes is determined by display
list mechanism which allows for multiple boxes,
background loading, fast switching, scrolling and fading
of regions
Support of 2, 4, 8-bit/pixel in fixed bit maps format or
coded in accordance to the DVB variable/run length
standard for region based graphics
Display colours are obtained via colour look up tables.
CLUT output is YUVT at 8-bit for each signal component
thus enabling 16 M different colours and 6-bit for T
which gives 64 mixing levels with video,
(T = transparency).
Bit-map table mechanism to specify a sub set of entries
if the CLUT is larger than required by the coded bit
pattern. Supported bit-map tables are 16 to 256,
4 to 256 and 4 to 16.
Graphics boxes may not overlap vertically. If 256 entry
CLUT has to be down loaded, a vertical separation of
1 line is mandatory.
Optimized memory utilization in MPEG video decoding
allows for a storage capacity of 1.2 Mbit for graphics bit
maps. Flexibility in memory control enables larger
capacity in a lot of applications. Moreover variable
length/run length encoding makes better use of
available memory capacity for graphics bit maps thus
making full screen graphics at 8-bit/pixel feasible.
Fast CPU access (9 Mbytes/s) enables full 1.2 Mbit bit
map update within 20 ms
Internal support for fast block moves in external SDRAM
Graphics mechanism can be used for signal generation
in the vertical blanking interval. Useful for teletext, wide
screen signalling, closed caption, etc.
Support for a single down loadable cursor of 1k pixel
with programmable shape. Supported shapes are
8
×
128 pixels, 16
×
64 pixels, 32
×
32 pixels,
64
×
16 pixels and 128
×
8 pixels.
Cursor colours obtained via 4 entry CLUT with YUVT at
6,4,4 respectively 2 bits. Mixing of cursor with
video + graphics in 4 levels.
Cursor can be moved freely across the screen without
overlapping restrictions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7212H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVG decoder |
| SAA7214 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Transport MPEG2 source decoder |
| SAA7215 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
| SAA7215HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
| SAA7215HS/C2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
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