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參數(shù)資料
| 型號： | SAA7157T-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 68K |
| 代理商： | SAA7157T-T |
May 1992
7
Philips Semiconductors
Product specication
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
Notes
1. fLFCO = 7.0 MHz and output load 40 pF (Fig.3). VSSA and VSSD short connected together.
2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter
components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more
than
±2 ns if output loads are matched within 20%.
3. MS and LFCO2 functions not tested.
Output signals LL1.5A, LL1.5B, LL3A and LL3B (pins 7, 10, 14, and 20); note 3
VOL
output voltage LOW
IO L = 2 mA
0
-
0.6
V
VOH
output voltage HIGH
IOH = 0.5 mA
2.6
-
VDDD
V
tcomp
composite rise time
Fig.3; notes 1 and 2 -
-
8
ns
fLL
output frequency LL1.5A
Fig.3
-
4 fLFCO(2)
MHz
output frequency LL1.5B
-
4 fLFCO(2)
MHz
output frequency LL3A
-
2 fLFCO(2)
MHz
output frequency LL3B
-
2 fLFCO(2)
MHz
tr, tf
rise and fall times
note 1; Fig.3
-
5
ns
tLL
duty factor LL1.5A, LL1.5B, LL3A
and LL3B (mean values)
note 1; Fig.3;
at 1.5 V level
43
50
57
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.3 Output timing.
handbook, full pagewidth
MEH456
tHD
tSU
tLL1.5H
tLL1.5L
tLL1.5
2.4 V
0.6 V
2.6 V
1.5 V
0.6 V
2.6 V
1.5 V
0.6 V
tr
tf
tcomp
tf
tLL3L
tLL3H
tLL3
LL3A
LL3B
LL1.5A
LL1.5B
CREF
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