參數(shù)資料
型號(hào): SAA5281GP
廠商: NXP SEMICONDUCTORS
元件分類: 圖文
英文描述: RES 11.3K OHM 1/16W .5% 0603 SMD
中文描述: TELETEXT AND VPS/PDC DECODER, PQFP64
封裝: 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-319-2, QFP-64
文件頁(yè)數(shù): 12/48頁(yè)
文件大?。?/td> 1187K
代理商: SAA5281GP
1996 Nov 04
12
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes
1.
This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to
±
1 mA.
Voltage level V
OH
for R, G and B outputs is taken to be the mean value during the output HIGH time. If higher R, G
and B voltage V
OH
levels are required RGBREF voltage level may be raised and a pull-up resistor used at each of
these pins provided current specification (I
OL
) is not exceeded.
2.
ODD/EVEN
OR
DV
V
OL
V
OH
C
L
t
r
LOW level output voltage
HIGH level output voltage
load capacitance
output rise time
I
OL
= 1.6 mA
I
OH
=
1.6 mA
0
V
DD
0.4
0.4
V
DD
120
50
V
V
pF
ns
between 0.6 V and
2.2 V
between 0.6 V and
2.2 V
t
f
output fall time
50
ns
COR
AND
Y (
OPEN
-
DRAIN OUTPUTS
)
V
OH
HIGH level pull-up output
voltage
LOW level output voltage
V
DD
V
V
OL
I
OL
= 2 mA
I
OL
= 5 mA
0
0
0.4
1.0
25
50
V
V
pF
ns
C
L
t
f
load capacitance
output fall time
load resistor of 1.2 k
to V
DD
; measured
between V
DD
0.5 V
and 1.5 V
V
I
= 0 to V
DD
I
LO
t
skew
output leakage current
skew delay between display
outputs R, G, B, COR, Y and
BLAN
10
+10
20
μ
A
ns
I
2
C-bus timing
(see Fig.5)
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
SU;STO
SCL clock LOW time
SCL clock HIGH time
data set-up time
data hold time
set-up time from clock HIGH
to STOP
START set-up time following a
STOP
START hold time
START set-up time following a
clock LOW-to-HIGH transition
4.0
4.0
250
170
4.0
μ
s
μ
s
ns
ns
μ
s
t
BUF
4.0
μ
s
t
HD;STA
t
SU;STA
4.0
4.0
μ
s
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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SAA5284GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia video data acquisition circuit
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