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參數(shù)資料
| 型號： | SAA2520GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Stereo filter and codec for MPEG layer 1 audio applications |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 14 X 14 X 2.20 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 151K |
| 代理商： | SAA2520GP |
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August 1993
11
Philips Semiconductors
Preliminary specification
Stereo filter and codec for MPEG layer 1
audio applications
SAA2520
Interface between SAA2520 and SAA2521 consists of the following signals:
F
ILTERED
-I
2
S
INTERFACE
SWS
SCL
FDAC
FDAF
FSYNC
bi-directional
bi-directional
bi-directional
bi-directional
output
word select (common to I
2
S)
bit clock (common to I
2
S)
codec data
filter data
synchronization
FS
64FS
FS/32
Filtered data is transferred between SAA2520 filter/codec
functions and the SAA2521 using the format shown in
Fig.9.
The frequency of the SWS signal is equal to the sample
frequency FS and the bit clock SCL is 64 times the sample
frequency. Each period of SWS contains 64 data-bits, 48
of which are used to transfer data. The half period in which
SWS is LOW is used to transfer the information of the
LEFT channel while the following half period during which
SWS is HIGH carries the data of the RIGHT channel.
The 24-bit samples are transferred most significant bit first.
This bit is transferred in the bit clock period with a 1-bit
delay following the change in SWS. Both SWS and
FDAF/FDAC change state at the negative edge of SCL.
The SAA2521 may be synchronized to the sub-band
codec using the FSYNC signal, which defines the SWS
period in which the samples of sub-band 0 (containing the
lowest frequency components) are transferred
(see Fig.10).
SAA2521
AND INPUT
/
OUTPUT MODE CONTROL
The operation of SAA2521 and the input/output circuitry is
controlled by three signals shown in Table 1.
FRESET and SYNCDAI are given whenever:
FS256, SCL and SWS outputs switch between
high and low impedance
FS256 frequency is changed
(12.288/11.2896/8.192 MHz)
FDIR is switching
bit rate is changing
system reset is active
MPEG C
ODED
I
NTERFACE
The interface that carries the MPEG coded signal uses
the following signals:
The MPEG I
2
S interface
The SBMCLK signal is the main frequency from which
other clock signals are derived. In encode mode this
division is performed internally. In decode mode the
external source should provide SBWS and SBCL.
The frequency of the signal is equal to 1/32nd of the bit
rate. The frequency of the bit clock SBCL is twice that of
the bit rate. Some examples of the frequencies are given
in Table 2.
SBWS
SBCL
SBDA
SBEF
Operation is further controlled by:
SBDIR
input
URDA
input
bi-directional
bi-directional
bi-directional
input
word selection
bit clock
sub-band coded data
error signal
direction of data flow
unreliable encoded data signal
相關(guān)PDF資料 |
PDF描述 |
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| SAA2520 | Stereo filter and codec for MPEG layer 1 audio applications |
| SAA3004 | Remote control transmitter |
| SAA3004P | Remote control transmitter |
| SAA3004T | Remote control transmitter |
| SAA3007 | INFRARED REMOTE CONTROL TRANSMITTER (LOW VOLTAGE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2521 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Masking threshold processor for MPEG layer 1 audio compression applications |
| SAA2521GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Masking threshold processor for MPEG layer 1 audio compression applications |
| SAA2531DEB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| SA-A2870-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Differential Positive ECL (DPECL) |
| SA-A2871-FREQ | 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:Differential Positive ECL (DPECL) |
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