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參數(shù)資料
| 型號(hào)： | SAA2500H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | MPEG Audio Source Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 15/47頁 |
| 文件大?。?/td> | 199K |
| 代理商： | SAA2500H |
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September 1994
15
Philips Semiconductors
Preliminary specification
MPEG Audio Source Decoder
SAA2500
Table 8
Signals of coded data slave input interface.
SIGNAL
DIRECTION
FUNCTION
CDS
CDSEF
CDSCL
CDSWA
CDSSY
input
input
input
input
input
ISO/MPEG coded input data (slave input)
coded data (slave input) error flag
coded data (slave input) clock
coded data (slave input) burst windowing signal
coded data (slave input) frame sync
Fig.8 Input data serial transfer format (slave input).
CDSSY indicates frame start during valid data.
handbook, full pagewidth
CDSWA
CDSCL
CDSSY
MGB496
CDSEF
CDS
valid data
valid but unreliable data
invalid data
frame start
1 unreliable data bit (example)
CDS is the SAA2500 input data bitstream. Data clock
CDSCL must have a frequency equal to or higher than the
bit rate. The maximum CDSCL frequency is 768 kHz. Error
flag CDSEF is handled in the same way as CDMEF is
handled for the master input (in Fig.8, one unreliable data
bit is shown as an example). The value of CDSEF is
neglected for those bits where CDSWA is LOW. Window
signal CDSWA being HIGH indicates valid data; in this
way, burst input data is allowed. The constraints for the
ability to use ‘burst signals’ are explained below. Frame
sync signal CDSSY indicates the start of each input data
frame. CDSSY is synchronous with CDSCL. CDSSY may
be present or not: as described below. The first valid CDS
bit after a leading edge of CDSSY is interpreted to be the
first frame bit.
The minimum time for CDSSY to stay HIGH is one CDSCL
period; the maximum HIGH period is constrained by the
requirement that CDSSY must be LOW at least during one
CDSCL period per frame (a leading edge, i.e. a frame start
indication, must be present every frame). Leading edges
of CDSSY can occur while CDSWA is HIGH, as in Fig.8.
Alternatively, a situation as shown in Fig.9 is also allowed,
where CDSSY has a leading edge while CDSWA is LOW,
i.e. during invalid data. The first CDS bit after CDSWA
going HIGH is now interpreted to be the first frame bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA2501 | Digital Audio Broadcast DAB decoder |
| SAA2501H | Digital Audio Broadcast DAB decoder |
| SAA2502 | ISO/MPEG Audio Source Decoder |
| SAA2502H | ISO/MPEG Audio Source Decoder |
| SAA2503 | MPEG2 audio decoder(MPEG2 音頻譯碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2500HB-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Processing/ENDEC for MPEG |
| SAA2501 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Audio Broadcast DAB decoder |
| SAA2501H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Audio Broadcast DAB decoder |
| SAA2501HB-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio Decoder & Support |
| SAA2502 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/MPEG Audio Source Decoder |
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