參數(shù)資料
型號： SAA2022GP
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Tape formatting and error correction for the DCC system
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, SOT-208A, QFP-64
文件頁數(shù)： 30/52頁
文件大?。?/td> 208K
代理商： SAA2022GP
February 1994
30
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
Table 4
Microcontroller Interface Commands.
CMD
REGISTER
76543210
COMMAND
EXPLANATION
XXXX1000
RDAUX
read AUXILIARY INFO
XXXX1001
RDSYS
read SYSINFO
XXXX1010
WRAUX
write AUXILIARY INFO
XXXX1011
WRSYS
write SYSINFO
XXXX0000
LDSET0
load new settings register 0
XXXX0001
LDSET1
load new settings register 1
XXXX0010
LDAFLEV
load AUX flag threshold level
XXXX0011
LDSPDDTY
load record speed duty cycle
XXXX0101
LDBYTCNT
load byte counter
XXXX0110
LDRACCNT
load random access counter
XXYZ1100
RDDRAC
read data in random access mode from RAM quarter YZ
XXYZ1101
RDFDRAC
read flag and data in random access mode from RAM quarter YZ
XXYZ1110
WRDRAC
write data in random access mode to RAM quarter YZ
XXYZ1111
WRFDRAC
write flag and data in random access mode to RAM quarter YZ
Explanation of settings
SET0 R
EGISTER
(T
ABLE
6)
μ
CSPD
An active HIGH, selects microprocessor control for the
SPEED pulse width modulated servo control signal.
DISRSY
Disable Resyncs active HIGH, is used in after recording.
RECLAB
Record labels active HIGH when in DRAR or DPAR
modes; a label being defined as the bodies of all four AUX
tape blocks in a tape frame which is being written.
This setting has immediate effect and should only be
modified in time segment 1.
ENFREG
In modes DPAP and DPAR Enable Frequency Regulation
active HIGH, allows frequency information from the data
channels to be used with the phase information to
generate the capstan SPEED signal.
ENEFREG
Enable Extended Frequency Regulation active HIGH,
allows extended frequency information from the data
channels to be used with the “normal” frequency
information and the phase information to generate the
capstan SPEED signal, if ENFREG is active.
SET1 R
EGISTER
(T
ABLE
7)
TEST1
This setting is for test only. For use in applications this bit
should be always programmed to logic 0.
PINO1
Pin Output 1, Port expander output for the microcontroller.
TFEMAS
This allows the SAA2022 to become master of the
SB-I
2
S-bus in modes DPAP and DPAR. In mode DRAR
the device always operates as a slave irrespective of the
settings bit.
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