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參數(shù)資料
| 型號： | SAA1101 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Universal sync generator USG |
| 中文描述： | 通用同步發(fā)電機副秘書長 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 112K |
| 代理商： | SAA1101 |
January 1990
7
Philips Semiconductors
Product specication
Universal sync generator (USG)
SAA1101
LOCK WITH HORIZONTAL AND VERTICAL SIGNALS
(slow lock modes only)
It is possible to use horizontal and vertical signals instead of composite sync signals. The connections in this situation
are: the external horizontal signal is connected to the ECS input (pin 11) and the vertical signal to the RR input (pin 12).
The HIGH time of the horizontal pulse must be less than 14.4
s, otherwise it will be detected as being a vertical pulse
and will corrupt the vertical slow lock system.
Selection of Clock Frequency
The clock frequency is selected using the CS0 and CS1 inputs as illustrated below.
Where the horizontal frequency, fH = 15.625 kHz for 625 lines and 15.734264 kHz for 525 lines.
Oscillators
The subcarrier oscillator has FSI as its input and FSO as its output. It is always used as a crystal oscillator with a series
resonance crystal with parallel load capacitor. The maximum frequency, fmax = 5 MHz and the load capacitor,
CL =10 < CL < 35 pF.
The clock oscillator has OSCI as its input and OSCO as its output. It can be used with an LC oscillator or a series
resonance crystal with parallel load capacitor (Fig.4). The maximum frequency, fmax = 24 MHz and the load capacitor,
CL = 10 < CL < 35 pF.
Selection of 625/525 (standard; interlaced mode) or 624/524 lines (non-interlaced mode)
Selection is achieved using the NORM input. When NORM = 0, 625/525 (standard) lines are selected;
when NORM = 1, 624/524 line are selected.
Output Dimensions
All push-pull outputs: standard output 2 mA.
White measurement pulse, WMP: 3-state output 2 mA.
Phase detector, PH: 3-state output 2 mA.
CS0
CS1
FREQUENCY
625 LINES
525 LINES
UNITS
0
160fH
2.5
2.517482
MHz
0
1
160fH
5
5.034964
MHz
1
0
960fH
15
15.104893
MHz
1
1440fH
22.5
22.657340
MHz
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