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參數(shù)資料
| 型號(hào)： | SA571N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Compandor |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDIP16 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | SA571N |
Philips Semiconductors
Product specification
SA571
Compandor
1997 Aug 14
7
0
3
10k
1MEG
INPUT = 0dBm
–20dBm
–40dBm
FREQUENCY (Hz)
G
SR00686
Figure 12. Rectifier Frequency Response vs Input Level
VARIABLE GAIN CELL
Figure 13 is a diagram of the variable gain cell. This is a linearized
two-quadrant transconductance multiplier. Q
1
, Q
2
and the op amp
provide a predistorted drive signal for the gain control pair, Q
3
and
Q
4
. The gain is controlled by I
G
and a current mirror provides the
output current.
The op amp maintains the base and collector of Q
1
at ground
potential (V
REF
) by controlling the base of Q
2
. The input current I
IN
(=V
IN
/R
2
) is thus forced to flow through Q
1
along with the current I
1
,
so I
C1
=I
1
+I
IN
. Since I
2
has been set at twice the value of I
1
, the
current through Q
2
is:
I
2
-(I
1
+I
IN
)=I
1
-I
IN
=I
C2
.
The op amp has thus forced a linear current swing between Q
1
and
Q
2
by providing the proper drive to the base of Q
2
. This drive signal
will be linear for small signals, but very non-linear for large signals,
since it is compensating for the non-linearity of the differential pair,
Q
1
and Q
2
, under large signal conditions.
Q
1
Q
2
Q
3
Q
4
IOUT
IG
I1
IIN
IGVIN
I2R2
NOTE:
I
2
(= 2I
1
)
280
μ
A
I
G
I
IN
V
IN
R
2
20k
I
1
140
μ
A
V+
V–
SR00687
Figure 13. Simplified
G Cell Schematic
The key to the circuit is that this same predistorted drive signal is
applied to the gain control pair, Q
3
and Q
4
. When two differential
pairs of transistors have the same signal applied, their collector
current ratios will be identical regardless of the magnitude of the
currents. This gives us:
I
C1
I
C2
I
C4
I
C3
I
1
I
1
I
IN
I
IN
plus the relationships I
G
=I
C3
+I
C4
and I
OUT
=I
C4
-I
C3
will yield the
multiplier transfer function,
I
G
I
1
R
2
I
1
I
OUT
I
IN
V
IN
I
G
This equation is linear and temperature-insensitive, but it assumes
ideal transistors.
4
3
2
1
.34
–6
0
+6
4mV
3mV
2mV
1mV
INPUT LEVEL (dBm)
%
V
OS
= 5mV
SR00688
Figure 14.
G Cell Distortion vs Offset Voltage
If the transistors are not perfectly matched, a parabolic, non-linearity
is generated, which results in second harmonic distortion. Figure 14
gives an indication of the magnitude of the distortion caused by a
given input level and offset voltage. The distortion is linearly
proportional to the magnitude of the offset and the input level.
Saturation of the gain cell occurs at a +8dBm level. At a nominal
operating level of 0dBm, a 1mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than this,
which means our overall offsets are typically about mV. The
distortion is not affected by the magnitude of the gain control
current, and it does not increase as the gain is changed. This
second harmonic distortion could be eliminated by making perfect
transistors, but since that would be difficult, we have had to resort to
other methods. A trim pin has been provided to allow trimming of the
internal offsets to zero, which effectively eliminated
second harmonic distortion. Figure 15 shows the simple trim
network required.
Figure 16 shows the noise performance of the
G cell. The
maximum output level before clipping occurs in the gain cell is
plotted along with the output noise in a 20kHz bandwidth. Note that
the noise drops as the gain is reduced for the first 20dB of gain
reduction. At high gains, the signal to noise ratio is 90dB, and the
total dynamic range from maximum signal to minimum noise is
110dB.
3.6V
V
CC
R
20k
6.2k
To THD Trim
≈
200pF
SR00689
Figure 15. THD Trim Network
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