參數(shù)資料
型號： SA56
廠商： APEX MICROTECHNOLOGY CORP
元件分類： 運動控制電子
英文描述： PULSE WIDTH MODULATION AMPLIFIER
中文描述： STEPPER MOTOR CONTROLLER, 10 A, ZFM23
封裝： SIP-23
文件頁數(shù)： 5/7頁
文件大小： 510K
代理商： SA56
APEX MICROTECHNOLOGY CORPORATION TELEPHONE (520) 690-8600 FAX (520) 888-3329 ORDERS (520) 690-8601 EMAIL prodlit@apexmicrotech.com
5
OPERATING
CONSIDERATIONS
SA56
GENERAL
Please read Application Note 1 "General Operating Consid-
erations" which covers stability, power supplies, heat sinking,
mounting, and specification interpretation. Visit www.apexmi-
crotech.com for design tools that help automate tasks such as
calculations for stability, internal power dissipation, current limit,
heat sink selection, Apex's complete Application Notes library,
Technical Seminar Workbook and Evaluation Kits.
GROUND PINS
There are 4 GND pins. Pins 9 & 10 are for input signal GND
and pins 1 and 23 are for power gnd.
POWER SUPPLY BYPASSING
Bypass capacitors to power supply terminals Vs and V
must be connected physically close to the pins to prevent
erratic, low efficiency operation and excessive ringing at the
outputs. Electrolytic capacitors, at least 10μF per output amp,
are required for suppressing Vs to PGND noise. High qual-
ity ceramic capacitors (X7R) 1μF or greater should also be
used. Only capacitors rated for switching applications should
be considered.
The bypass capacitors must be located as close to the power
supply pins as possible (due to the very fast switching times
of the outputs, the inductance of 1 inch of circuit trace could
cause noticeable degradation in performance). The bypassing
requirements of V
are less stringent, but still necessary. A
0.1μF to 0.47μF capacitor connected directly between the V
DD
and GND (SIG) pins will suffice.
PIN DESCRIPTIONS
Pin #
Name
Description
1,23
PGND
Power ground, high current ground
return path of the motor.
2,3
Bout
Half bridge output B
4,5,19,20 VS
High voltage supply
6
SCin
Short circuit detect, CMOS. This pin
can be used as a flag for a short cir-
cuit condition. Under normal operation
this pin will be logic low. When a short
circuit is detected, or output current
exceeds approximately 10A, this pin
will change to logic high and the output
will be latched off. Grounding this pin
disables short circuit protection. This
pin should be left open if short circuit
protection is desired but the flag is not
used. Short circuit protection functions
independently of programmable current
limit (ISEN). It is nessesary to bypass
the SCin pin with a 14-47pF ceramic
capacitor. This capacitor will add a de-
lay to the short circuit response but the
device will still be able to protect itself
against short circuit and over current.
7
TLIM
Temperature limit, CMOS. This pin can
be used as a flag for an over temperature
condition. Under normal operation this
pin will be logic low. When junction tem-
perature exceeds approximately 160°C
this pin will change to logic high and
the output will be latched off. Ground-
ing this pin disables over temperature
protection. This pin should be left open
if over temperature protection is desired
but the flag is not used.
ISEN/ /ILIM Current Sense output and program-
mable current limit. A current propor-
tional to output current is sourced by
this pin. Typically this pin is connected
to a resistor for programmable current
limit or transconductance operation.
GND(Sig) Ground connection for all internal digital
and low current analog circuitry.
FAULT
Protection circuit flag output, CMOS.
The fault pin will be logic high when the
output MOSFETs have been automati-
cally latched off because of a short circuit
or over temperature condition. This pin
should be left open if not used.
CPWM
An external timing capacitor s connected
to this pin to set the frequency of the
internal oscillator and ramp generator
for analog control mode. The capaci-
tor value (pF) = 4.05x10
7
/F
, where
F
= the desired switching frequency.
This pin is grounded for digital control
mode.
VDD
5V supply for input logic and low voltage
analog circuitry.
VREF
Reference voltage. Can be used at
low current for biasing analog loop
circuits.
DIR
Direction logic input, CMOS/TTL. De-
termines the active output MOSFETs
in two quadrant digital control mode.
This pin should be grounded for analog
control mode.
PWM
CMOS/TTL input for digital PWM con-
trol, or 1-4V analog input for duty cycle
control in analog control mode.
DISABLE Disable logic input, CMOS/TTL. Logic
low on this pin allows the SA56 to func-
tion normally. When pulled to logic high,
all four output MOSFETs are disabled.
Pulling this pin high, then low will reset
a latched fault condition caused by a
short circuit or over temperature fault.
Aout
Half bridge output A
8
9,10
11
12
13,14
15
16
17
18
21,22
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