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參數(shù)資料
| 型號(hào)： | SA25F020LENFX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 27/37頁 |
| 文件大?。?/td> | 560K |
| 代理商： | SA25F020LENFX |
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SA25F020 Advanced Information
SAIFUN
27
Page
Erase
(PE)
The PE instruction sets all 256 bytes in the
selected page to 1. Before it can be
executed, two separate instructions must
be carried out. The device must first be
write enabled via the WREN instruction,
and then a PE sequence, which consists of
one opcode byte and three data bytes may
be executed. The address of the memory
locations to be written must be inside the
page to be erased and outside the
protected address field location selected by
the Block Write Protection level. During an
internal PE cycle, all commands are
ignored except the RDSR instruction.
A PE instruction requires the following
sequence:
1. After the CSb line is pulled low to
select the device, the PE opcode is
transmitted via the SI line, followed
by the 3-byte address.
2. Erasing begins after the CSb pin is
brought
high.
low-to-high transition must occur
during
the
SCK
immediately after the clock in the
last address bit.
The CSb pin's
low
time,
As soon as CSb is driven high, the
self-timed PE cycle (whose duration is
defined as T
PE
) is initiated. While the PE
cycle is in progress, the status register may
be read to check the value of the /RDY bit.
The /RDY bit is 1 during the self-timed PE
cycle, and 0 when it is completed. The
WEN bit is reset at some unspecified time
before the cycle is completed. The
instruction sequence is shown in Figure 17.
The SA25F020 is automatically returned to
the Write Disable state at the completion of
a PE cycle.
NOTES:
1. If the device is not write enabled,
the
device
ignores
instruction and returns to the
standby state when CSb is brought
high. A new CSb falling edge is
required to re-initiate the serial
communication.
2. A PE instruction applied to a page
that is protected by the Block
Protect
(BP1,
described in Table 8, page 18, and
Table 9, page 21) is not executed.
the
PE
BP0)
bits
(as
1
3
2
10
9
8
7
6
5
4
0
31
30
29
28
Instruction
24 Bit Address
1
3
2
0
SCK
SI
MSB
CS
23
21
22
Figure 17. Page Erase (PE) Instruction Sequence
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