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參數(shù)資料
| 型號： | SA2400ABE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Single chip transceiver for 2.45 GHz ISM band |
| 中文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大?。?/td> | 325K |
| 代理商： | SA2400ABE |
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Philips Semiconductors
Product data
SA2400A
Single chip transceiver for 2.45 GHz ISM band
2002 Nov 04
19
14.2 Description of READ cycle
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
enabled.
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
The bit values on SDATA are taken over with rising edges on
SCLK.
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising
edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.
4. (SCLK edges 9 through 32) 24 data bits are clocked out, LSB
first. The bits will be available on the SDATA pin with the falling
edges of SCLK (so bits can be accepted by the baseband IC
with the following rising edge).
1
2
3
4
5
6
7
8
9
10
11
32
1
A0
A1
A2
A3
A4
A5
A6
R/W
D0
D1
D2
D23
T
on
T
setup
T
hold
T
cyc
t
r
t
f
SCLK
SEN
SDATA
SR02289
T
dout
Figure 10.
READ cycle timing diagram of the 3-wire bus
The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new data even during power-down. The
data remains latched during power-down (sleep mode).
14.3 3-wire bus/logic control AC characteristics
Table 11. 3-wire bus/logic control AC characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
Min
Typ
Max
Serial Bus Logic Level Requirements
V
IH
V
IL
Serial Programming Clock, SCLK
HIGH logic input voltage
0.5
×
V
DD
–0.3
–
V
DD
+ 0.3
0.2
×
V
DD
V
LOW logic input voltage
–
V
t
r
t
f
T
cyc
Enable Programming, SEN
Input rise time
–
10
40
ns
Input fall time
–
10
40
ns
Clock period
22
100
–
ns
T
on
Data Programming, SDATA
Delay to rising clock edge
10
–
–
ns
T
setup
T
hold
T
dout
Input data to clock set-up time
–
10
–
–
ns
Input data to clock hold time
–
10
–
–
ns
Output data to clock delay time
(
falling edge)
–
–
–
10
ns
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