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參數(shù)資料
| 型號： | SA1638 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage IF I/Q transceiver |
| 中文描述： | 低電壓中頻I / Q收發(fā)器 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 291K |
| 代理商： | SA1638 |
Philips Semiconductors
Product specification
SA1638
Low voltage IF I/Q transceiver
1997 Sept 03
8
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNITS
MIN
–3
σ
+3
σ
MAX
IF Synthesizer (cont.)
I
CP
I
CP
Relative output current variation
4
I
REF
=31.2
μ
A
0.1
1.3
2.5
±
10
%
I
CP_M
Output current matching
5
I
REF
=31.2
μ
A,
V
CP
= V
CC
CP/2
V
CP
= 0.3V to V
CC
CP-0.3V
POnPLL = HI, to full charge
pump current
POnPLL = LO, to I
CC
CP,
I
CC
DIG <5% of operational
supply current
±
12
%
|I
CP_L
|
Output leakage current
-0.02
0.1
0.22
±
15
nA
t
ON
Turn ON time
15
μ
s
t
OFF
Turn OFF time
6
15
μ
s
Serial Interface
7
f
CLOCK
Clock frequency
Set-up time: DATA to CLOCK,
CLOCK to STROBE
Hold time: CLOCK to DATA
Pulse width: CLOCK
Pulse width: STROBE
10
MHz
t
SU
30
ns
t
H
30
30
30
ns
t
W
ns
NOTES:
1. Parameter measured relative to modulation sideband amplitude.
2. After programming the DC offset register for minimum offset. DCRES = 562k
.
3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for
GSM–mode = 8
μ
s with filter bandwidth setting resistor = 36k
).
4. The relative output current variation is defined thus:
I
OUT
5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on.
6. As soon as P
PLL is set to LO, the phase detector is reset and no charge pumps pulses are generated.
7. Guaranteed by design.
I
OUT
2
(I
2
|(I
2
I
1
)
I
1
)|; with V
1
= 0.3V, V
2
= V
CC
CP – 0.3V (see Figure 3).
8. NF =
20log
E
no
4kTR
VG where, E
no
is the output noise voltage measured in a 1Hz bandwidth, R = 1200
, VG = gain in dB.
9. Minimium frequency is guaranteed by design.
I
2
I
1
I
2
I
1
V
1
V
2
CURRENT
VOLTAGE
SR00526
Figure 3. Relative Output Current Variation
FUNCTIONAL DESCRIPTION
Serial Programming Input
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status- and
DC-offset register, mode select and test register. The programming
data is structured into two 21-bit words; each word includes 4 chip
address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,
the clock is disabled and the data in the shift register remains stable.
Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.
Default States
Upon power up (V
CC
DIG is applied) a reset signal is generated,
which sets all registers to a default state. The logic level at the
STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 3.
Reference Divider
The reference divider can be programmed to four different division
ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide
by 13.
Main Divider
The external VCO signal, applied to the LO
IN
and LO
IN
X inputs, is
divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is
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