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參數(shù)資料
| 型號： | SA08_06 |
| 廠商： | Apex Microtechnology Corporation |
| 英文描述： | PULSE WIDTH MODULATION AMPLIFIERS |
| 中文描述： | 脈寬調(diào)制放大器 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 233K |
| 代理商： | SA08_06 |
APEX MICROTECHNOLOGY CORPORATION 5980 NORTH SHANNON ROAD TUCSON, ARIZONA 85741 USA APPLICATIONS HOTLINE: 1 (800) 546-2739
4
adjusted so as to
reduce the switch-
ing noise well below
100 mV to prevent
false current limit-
ing. The sum of the
DC level plus the
noise peak will de-
termine the current
limiting value. As
in most switching
circuits it may be
difficult to deter-
mine the true noise
amplitude without
careful attention to
grounding of the oscilloscope probe. Use the shortest possible
ground lead for the probe and connect exactly at the GND
terminal of the amplifier. Suggested starting values are C
FILTER
= .1uF, R
FILTER
= 5k .
The required value of R
LIMIT
in voltage mode may be cal-
culated by:
R
LIMIT
= .1 V / I
LIMIT
where R
is the required resistor value, and I
is the
maximum desired current. In current mode the required value
of each R
is 2 times this value since the sense voltage is
divided down by 2 (see Figure B). If R
is used it will further
divide down the sense voltage. The shutdown divider network
will also have an effect on the filtering circuit.
BYPASSING
Adequate bypassing of the power supplies is required for
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the out-
puts. The Vs supply should be bypassed with at least a 1μF
ceramic capacitor in parallel with another low ESR capacitor
of at least 10μF per amp of output current. Capacitor types
rated for switching applications are the only types that should
be considered. The bypass capacitors must be physically
connected directly to the power supply pins. Even one inch of
lead length will cause excessive ringing at the outputs. This is
due to the very fast switching times and the inductance of the
lead connection. The bypassing requirements of the Vcc supply
are less stringent, but still necessary. A .1μF to .47μF ceramic
capacitor connected directly to the Vcc pin will suffice.
STARTUP CONDITIONS
The high side of the IGBT output bridge circuit is driven by
bootstrap circuit and charge pump arrangement. In order for
the circuit to produce a 100% duty cycle indefinitely the low
side of each half bridge circuit must have previously been in
the ON condition. This means, in turn, that if the input signal
to the SA08 at startup is demanding a 100% duty cycle, the
output may not follow the command and may be in a tri-state
condition. The ramp signal must cross the input signal at
some point to correctly determine the output state. After the
ramp crosses the input signal level one time, the output state
will be correct thereafter.
OPERATING
CONSIDERATIONS
SA08
GENERAL
Please read Application Note 30 on "PWM Basics". Refer
to Application Note 1 "General Operating Considerations" for
helpful information regarding power supplies, heat sinking and
mounting. Visit www.apexmicrotech.com for design tools that
help automate pwm filter design; heat sink selection; Apex’s
complete Application Notes library; Technical Seminar Work-
book; and Evaluation Kits.
CLOCK CIRCUIT AND RAMP GENERATOR
The clock frequency is internally set to a frequency of ap-
proximately 45kHz. The CLK OUT pin will normally be tied to
the CLK IN pin. The clock is divided by two and applied to an
RC network which produces a ramp signal. An external clock
signal can be applied to the CLK IN pin for synchronization
purposes, but must be 45 kHz +/- 2%.
FLAG OUTPUT
Whenever the SA08 has detected a fault condition, the flag
output is set high (10V). When the programmable low side cur-
rent limit is exceeded, the FLAG output will be set high. The
FLAG output will be reset low on the next clock cycle. This
reflects the pulse-by-pulse current limiting feature. When the
internally-set high side current limit is tripped or the thermal
limit is reached, the FLAG output is latched high. See PRO-
TECTION CIRCUITS below.
PROTECTION CIRCUITS
A fixed internal current limit senses the high side current.
Should either of the outputs be shorted to ground the high side
current limit will latch off the output transistors. The temperature
of the output transistors is also monitored. Should a fault con-
dition raise the temperature of the output transistors to 165°C
the thermal protection circuit latch off the output transistors.
The latched condition can be cleared by either recycling the
V
power or by toggling the I LIMIT/SHDN input with a 10V
pulse. See Figures A and B. The outputs will remain off as
long as the shutdown pulse is high (10V).
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connec-
tion (see figures A and B). It is recommended that R
resistors
be non-inductive. Load current flows in the I SENSE pins. To
avoid errors due to lead lengths connect the I LIMIT/SHDN pin
directly to the R
resistors (through the filter network and
shutdown divider resis-
tor) and connect the
R
resistors directly
to the GND pin.
Switching noise
spikes will invariably be
found at the I SENSE
pins. The noise spikes
could trip the current
limit threshold which
is only 100 mV. R
and C
FILTER
should be
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SA08U REV E OCTOBER 2006 2006 Apex Microtechnology Corp.
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