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參數(shù)資料
| 型號(hào)： | S93463SBT |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision Supply-Voltage Monitor and Reset Controller |
| 中文描述： | 精密電源電壓監(jiān)控和復(fù)位控制器 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 158K |
| 代理商： | S93463SBT |
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3
S93462/S93463
2021 4.2 1/23/01
Summit Microelectronics, Inc.
The format for all instructions is: one start bit; two op
code bits and either six (x16) or seven (x8) address or
instruction bits.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the S93462/463
will come out of the high impedance state and, will first
output an initial dummy zero bit, then begin shifting out
the data addressed (MSB first). The output data bits
will toggle on the rising edge of the SK clock and
are stable after the specified time delay
(t
PD0
or t
PD1
).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of 250ns (t
CSMIN
). The falling edge of CS will
start automatic erase and write cycle to the memory
location specified in the instruction. The ready/busy
status of the S93462/463 can be determined by select-
ing the device and polling the DO pin.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deselected for a minimum
of 250ns (t
CSMIN
). The falling edge of CS will start the
auto erase cycle of the selected memory location. The
ready/busy status of the S93462/463 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the content of a cleared location returns
to a logical
“
1
”
state.
Figure 1. Sychronous Data Timing
Figure 2. Read Instruction Timing
SK
2021 ILL 3 1.0
DI
CS
DO
tDIS
tPD0,tPD1
tCSMIN
tCSS
tDIS
tDIH
tSKHI
tCSH
VALID
VALID
DATA VALID
tSKLOW
SK
2021 ILL4 1.0
CS
DI
DO
tCS
STANDBY
tHZ
HIGH-Z
HIGH-Z
1
1
0
AN
AN
–
1
A0
0
DN
DN
–
1
D1
D0
tPD0
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