參數(shù)資料
型號: S83C196MH
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝: SHRINK, QFP-80
文件頁數(shù): 16/41頁
文件大?。?/td> 1547K
代理商: S83C196MH
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
23
EXPLANATION OF AC SYMBOLS
Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal
and its condition, respectively. Symbols represent the time between the two signal/condition points. For example,
T
RHDZ is the time between signal R (RD#) condition H (high) and signal D (Input Data) condition Z (floating). Table
10 defines the signal and condition codes.
AC CHARACTERISTICS (OVER SPECIFIED OPERATION CONDITIONS)
Table 11 defines the AC timing specifications that the external memory system must meet and those that the
8XC196MH will provide.
Table 10. AC Timing Symbol Definitions
Signals
Conditions
A
Address
P
PROG#
H
High
B
BHE#
Q
Data Out
L
Low
D
Data In
R
RD#
V
Valid
G
BUSWIDTH
V
PVER
X
No Longer Valid
I
T1DIR/AINC#
W
WR#/WRH#/WRL#
Z
Floating
K
T1CLK
X
XTAL1
L
ALE/ADV#/PALE#
Y
READY
Table 11. AC Timing Definitions (1)
Symbol
Parameter
Min
Max
Units
Notes
F
OSC
Frequency on XTAL1
8
16
MHz
T
OSC
1/F
OSC
62.5
125
ns
The External Memory System Must Meet These Specifications
T
AVYV
Address Valid to READY Setup
2T
OSC – 75
ns
T
LLYV
ALE/ADV# Low to READY Setup
T
OSC – 70
ns
T
YLYH
Non READY Time
No Upper Limit
ns
T
LLYX
READY Hold after ALE/ADV# Low
T
OSC – 15
2T
OSC – 40
ns
T
AVGV
Address Valid to BUSWIDTH Setup
2T
OSC – 75
ns
T
LLGV
ALE/ADV# Low to BUSWIDTH Setup
T
OSC – 60
ns
NOTES:
1.
Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, F
OSC = 16 MHz.
2.
Exceeding the maximum specification causes additional wait states.
3.
If wait states are used, add 2T
OSC × n, where n = number of wait states.
4.
Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
5.
Assuming back-to-back bus cycles.
6.
8-bit bus only.
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