參數(shù)資料
型號(hào)： S6C0679
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 6 BIT 420 CHANNEL RSDS TFT-LCD SOURCE DRIVER
中文描述： 6位420通道區(qū)特別職務(wù)隊(duì)的TFT - LCD源驅(qū)動(dòng)
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 188K
代理商： S6C0679
6 BIT 420 CHANNEL RSDS TFT–LCD SOURCE DRIVER PREMILINARY VER 1.0
S6C0679
7
PIN DESCRIPTIONS
Symbol
Pin Name
Description
VDD1
VDD2
VSS1
VSS2
Y1 to Y420
D0P<0:2>
D0N<0:2>
D1P<0:2>
D1N<0:2>
D2P<0:2>
D2N<0:2>
Logic power supply
Driver power supply
Logic ground
Driver ground
Driver outputs
2.7 to 3.6 V
7.0 to 10.5 V
Ground (0 V)
Ground (0 V)
The D/A converted 64 gray-scale analog voltage is output.
RSDS data input
Total data lines consist of 18 data bus.
(6-bit digital, 3 colors (R, G, B) and 2 differential input pairs)
The 3 - bit differential input pairs generate the internal 6 - bit data
through the comparison between DxxP and DxxN.
SHL
Shift direction
control input
This pin controls the direction of shift register in cascade connection.
When SHL = H: DIO1 input, Y1
→
Y420, DIO2 output
When SHL = L: DIO2 input, Y420
→
Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL = L: No inversion
DATPOL = H: Data polarity inversion (H
L)
POL = H: The reference voltage for odd number outputs are VGMA1 to
VGMA5 and those for even number outputs are VGMA6 to VGMA10.
POL = L: The reference voltage for odd number outputs are VGMA6 to
VGMA10 and those for even number outputs are VGMA1 to VGMA5.
The RSDS clock input pairs generate the internal shift clock, CLK2,
through the comparison between CLKP and CLKN.
S6C0679 clears 140 shift registers at the rising edge of CLK1 and
outputs the analog data to the each channel at the falling edge.
Input the gamma corrected power supplies from external source.
VDD2 > VGMA1 > VGMA2 >
……
> VGMA9 > VGMA10 > VSS2
Keep power supplies unchanged during the gray-scale voltage output.
The Structure of the line-repair amp is the same as that of the analog
output. RPI1 (RPI2)
→
impedance changed
→
RPO1 (RPO2)
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15 k
)
DIO1
Start pulse input / output
DIO2
Start pulse input / output
DATPOL
Data inversion input
POL
Polarity input
CLKP
CLKN
RSDS shift clock input
CLK1
Latch input
VGMA1
to VGMA10
Gamma corrected
power supplies
RPI1, RPO1
RPI2, RPO2
Line-repair AMP
input / output
TEST
Test input
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