參數(shù)資料
型號(hào): S6B0719
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 160 SEG / 105 COM SEG DRIVER & CONTROLLER FOR STN LCD
中文描述: 160賽格/ 105的COM賽格驅(qū)動(dòng)
文件頁(yè)數(shù): 17/64頁(yè)
文件大小: 575K
代理商: S6B0719
160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.4
S6B0719
14
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 105-row by 160-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 105 rows are divided into 13 pages of 8
lines and the 13th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly
through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common
lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the
LCD controller operates independently, data can be written into RAM at the same time as data is being displayed
without causing the LCD flicker.
COM0
COM1
COM2
COM3
COM4
- -
- -
- -
- -
- -
DB0
DB1
DB2
DB3
DB4
0
1
0
1
0
0
0
1
0
0
1
0
1
1
0
- -
- -
- -
- -
- -
0
1
0
0
1
Display Data RAM LCD Display
Figure 6. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 13 (DB3, DB2 and DB0 are “H”, but
DB1 is “L”) is a special RAM area for the icons and display data DB0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 7. It incorporates 7-bit line address register changed by only the
initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
160-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU
can not access Line Address of icons.
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