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參數(shù)資料
| 型號： | S6B0086 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 80 CH SEGMENT / COMMON DRIVER FOR DOT MATRIX LCD |
| 中文描述： | 80甲烷段/常見的點(diǎn)陣液晶驅(qū)動(dòng) |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 324K |
| 代理商： | S6B0086 |
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S6B0086
80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD
8
PIN DESCRIPTION
Pin
I / O
Name
Function
Interface
VDD
Logical "High" input port (+5V
±
10%, +3V
±
10%)
VSS
0V (GND)
VEE
Power supply
Logical "Low" for high voltage part
Power
V0, V12,
V43, V5
I
LCD driver
output voltage
level
Bias supply voltage input to drive the LCD. Bias voltage divided
by the resistance is usually used as a supply voltage source
(refer to NOTE 2).
Power
SC1 - SC80
O
LCD driver
output
Display data output pin which corresponds to the respective latch
contents. One of V0, V12, V34 and V5 is selected as a display
driving voltage source according to the combination of the
latched data level and M signal (refer to NOTE 1).
LCD
CL2
I
Data shift
clock
Clock pulse input for the bi-directional shift register.
– In segment driver application mode, the data is shifted to 20 x
4-bit segment data shift
The clock pulse, which was input when the enable bit
(ELB/ERB) is in not active condition, is invalid.
– In common driver application mode, the data is shifted to 80-bit
common data bi-directional shift register by the CL1 clock.
Hence, this clock pin is not used (Open or connect this pin to
VDD).
Controller
M
I
AC signal for
LCD driver
output
Alternate signal input pin for LCD driving.
Normal frame inversion signal is input in to this pin.
Controller
CL1
I
Data latch
clock
– In segment driver application mode, this signal is used for
latching the shift register contents at the falling edge of this clock
pulse.
CL1 pulse "High" level initializes power-down function block.
– In common driver application mode, CL1 is used as a shifting
clock of common output data.
Controller
DISPOFFB
I
Display OFF
control
Control input pin to fix the driver output (SC1~SC80) to V0 level,
during "Low" value input. LCD becomes non-selected by V0 level
output from every output of segment drivers and every output of
common drivers.
Controller
CS
I
COM / SEG
mode control
When CS = "Low", S6B0086 is used as an 80-bit segment driver.
When CS = "High", S6B0086 is set to an 80-bit common driver
VDD / VSS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S6B0107 | 64CH COMMON DRIVER FOR DOT MATRIX LCD |
| S6B0108 | 64 CH SEGMENT DRIVER FOR DOT MATRIX LCD |
| S6B0708 | 64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD |
| S6B0716X01-C0C8 | CAT5E PATCH CORD 3 FOOT BLUE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S6B0107 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64 CH SEGMENT DRIVER FOR DOT MATRIX LCD |
| S6B0108 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64 CH SEGMENT DRIVER FOR DOT MATRIX LCD |
| S6B0708 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD |
| S6B0715 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD |
| S6B0715A01-B0CY | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD |
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