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參數(shù)資料
| 型號： | S5T8554B03-S0B0 |
| 元件分類： | 編解碼器 |
| 英文描述： | MU-LAW, PCM CODEC, PDSO16 |
| 封裝： | SOP-16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 260K |
| 代理商： | S5T8554B03-S0B0 |
CODEC FOR DIGITAL ANSWERING PHONE
S5T8554B
3
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Pin No
Symbol
Description
1VBB
VBB =
5V ± 5%
2
GNDA
Analog ground
3VFRO
Analog output of the receiver filter
4VCC
Vcc = + 5V
± 5%
5FSR
Receive frame sync pulse. 8kHz pulse train.
6DR
PCM data input
7BCLKR /
CLKSEL
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock
in normal operation and BCLKx is used for both TX and RX directions.
Alternately direct clock input available, vary from 64kHz to 2.048MHz.
8MCLKR /
PDN
When MCLKR is connected continuously high, the device goes powered down .
Normally connected continuously low, MCLKx is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input is available.
9MCLKXn
1.536MHz/1.544MHz or 2.048MHz clock input is available
10
BCLKX
May be vary from 64kHz 2.048MHz,
but BCLKx is externally tied with MCLKx in normal operation.
11
DX
PCM data output.
12
FSX
TX frame sync pulse. 8kHz pulse train.
13
TSX
Changed from high to low during the encoder timeslot. Open drain output.
14
GSX
Analog output of the TX input amplifier.
Used to set gain through external resistor between pin 14 to pin 15.
15
VFXI
Inverting input stage of the TX analog signal.
16
VFXI+
Non-inverting input stage of the TX analog signal.e
Characteristic
Symbol
Value
Unit
Positive Supply Voltage
Vcc
+7
V
Negative Supply Voltage
VBB
7V
Voltage at any Analog Input or Output
V I (A)
Vcc + 0.3 to VBB 0.3
V
Voltage at any Digital Input or Output
V I (D)
Vcc + 0.3 to GNDA 0.3
V
Operating Temperature Range
Ta
0 to +70
°C
Storage Temperature Range
TSTG
65 to +150
°C
Lead Temperature Range ( soldering, 10 sec )
TLEAD
300
°C
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