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參數(shù)資料
| 型號(hào)： | S5N8951X |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | G.dmt ADSL Analog Front End IC |
| 中文描述： | G.dmt ADSL模擬前端IC |
| 文件頁(yè)數(shù)： | 12/22頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | S5N8951X |
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12
S5N8951X
G.dmt ADSL Analog Front End IC
CONFIDENTIAL
Preliminary Information (Rev.1.0)
4.1.1
Register Map
4.1.1.1
Power Control
The power on/off control of AFE blocks on this chip is set by the PWR_CTL register, (XX000), as
described below:
PWR_CTL Register (A4A3A2A1A0=XX000)
DATA
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
RESET
VALUE
0
0
0
0
0
0
0
0
Power Control is as follow.
PC7
PC6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
PC5
0
0
0
0
0
0
1
0
0
PC4
0
0
0
0
0
1
0
0
0
PC3
0
0
0
0
1
0
0
0
0
PC2
0
0
0
1
0
0
0
0
0
PC1
0
0
1
0
0
0
0
0
0
PC0
0
1
0
0
0
0
0
0
0
HEX
0000
0001
0002
0004
0008
0010
0020
0040
0080
DESCRIPCION
Normal Operation
N/A
N/A
TX DAC Power Down
TX Filter & AGC Power Down
RX ADC Power Down
Rx Filter Power Down
Rx AGC Power Down
VCXO DAC Power Down
Adding Power Down (based on upper power down)
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0003
000C
0070
00FF
N/A
TX Path Power Down
Rx Path Power Down
Whole Chip Power Down
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