參數資料
型號: S5N8943B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: G.Lite ADSL Analog Front End IC
中文描述: G. Lite的ADSL模擬前端IC
文件頁數: 18/22頁
文件大?。?/td> 263K
代理商: S5N8943B
18
S5N8943B
G.Lite ADSL Analog Front End IC
CONFIDENTIAL
Preliminary Information (Rev.1.0)
4.2
Data Interface
4.2.1
Physical Interface
l
l
l
ADC and DAC data transmission between S5N8943B01 and S5N8944
Parallel Interface(S5N8944) : 29 pin (14 ADC bit data, 14 DAC bit data, MCLK)
Parallel Interface : 16 pin ( 7 ADC bit data, 7 DAC bit data, MCLK,AUXCLK)
S5N8944
(DMT)
S5N8943B01
(AFE)
MCLK
TX_DATA[13:0]
RX_DATA[13:0]
AUXCLK
4.2.2
Waveform
Figure 4.2.1 Waveform of 14bit parallel interface (TM1=0)
Figure 4.2.2 Waveform of 7bit parallel interface (TM1=1)
Parameter
Symbol
T
CYC
T
PWH
T
PWL
T
D
T
SU
T
H
T
SU2
T
H2
Min
Typ
226
113
113
Max
Unit
nS
nS
nS
nS
nS
nS
nS
nS
Note
MCLK Clock Period
MCLK High Time
MCLK Low Time
DATA Delay after MCLK
RX_DATA setup to MCLK
RX_DATA hold to MCLK
AUXCLK setup to MCLK
AUXCLK hold to MCLK
MCLK=4.416MHz
MCLK=4.416MHz
MCLK=4.416MHz
10
30
84
MCLK=4.416MHz
MCLK=4.416MHz
10
10
TX_DATA[13:0]
TX_DATA[13:0]
TX_DATA[13:0]
MCLK
TX_DATA
RX_DATA
TX_DATA[13:0]
RX_DATA[13:0]
RX_DATA[13:0]
T
PWH
T
PWL
T
D
T
D
T
SU
T
H
T
CYC
AUXCLK
TX_DATA[6:0]
TX_DATA[6:0]
MCLK
TX_DATA
TX_DATA13:7]
T
D
TX_DATA[13:7]
T
SU2
T
H2
RX_DATA[6:0]
RX_DATA[6:0]
RX_DATA
RX_DATA[13:7]
RX_DATA[13:7]
N- 1
N- 1
N
N
N- 1
N- 1
N
N
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相關代理商/技術參數
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S5N8944B 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:G.Lite ADSL Transceiver for CO and CPE
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