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參數(shù)資料
| 型號： | S3C8627XX-QZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, QFP-44 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 182K |
| 代理商： | S3C8627XX-QZ |
PRODUCT OVERVIEW
S3C8625/C8627/C8629/P8629
1-6
PIN DESCRIPTIONS
Table 1-1. S3C8625/C8627/C8629/P8629 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
SDIP Pin
Numbers
Shared
Functions
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
I/O
General-purpose, 8-bit I/O port. Shared
functions include three external interrupt
inputs and I/O for timer M0 and M1.
Selective configuration of port 0 pins to
input or output mode is supported.
D-1
1
2
3
4
5
6
7
8
INT0
INT1
INT2
TM0CAP
TM1CK
P1.0
P1.1
P1.2
I/O
General-purpose, 3-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-
drain mode, or IIC-bus clock and data I/O.
E-1
9
10
19
SDA1
SCL1
P2.0
P2.1
P2.2
P2.4
P2.5
P2.6
P2.7
I/O
General-purpose, 8-bit I/O port Selective
configuration of port 2 pins to input or
output mode is supported. The port 2 pin
circuits are designed to push-pull PWM
output and Csync signal input.
D-1
E-1
D-1
20
21
22
23
24
25
26
32
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
P3.0–P3.3
P3.4–P3.7
I/O
General-purpose, 8-bit I/O port Selective
configuration port 3 pins to input or output
mode is supported. Multiplexed for
alternative use as A/D converter inputs
AD0–AD3.
D-1
E
35–38,
39–42
AD0–AD3
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
SCL0
I
O
I/O
The pins are sync processor signal I/O, IIC-
bus clock, and data I/O.
A
G-3
31
30
27
28
29
16
17
–
V
DD, VSS1,
AVREF, V
SS2
–
Power pins
ADC power pins
–
11, 12
34, 33
–
XIN, XOUT
–
System clock I/O pins
–
14, 13
–
RESET
I
System reset pin
B
18
–
TEST
I
Factory test pin input
0V:Normal operation,5V:Factory test mode
–
15
–
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| S3C8629 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:S3C8625/C8627/C8629/P8629 MICROCONTROLLERS |
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