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參數(shù)資料
| 型號(hào)： | S3C8444XX-TW |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 18 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, TQFP-80 |
| 文件頁(yè)數(shù)： | 44/44頁(yè) |
| 文件大?。?/td> | 301K |
| 代理商： | S3C8444XX-TW |
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PRODUCT OVERVIEW
S3C8444
1–8
Table 1–1. S3C8444 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
P5.0–P5.7
I/O
General I/O port with nibble programmable
pins. Schmitt trigger input or push-pull,
open-drain output mode. Mode and pull-ups
are assigned by software.
3
10–3
—
P6.0–P6.7
O
N-channel, open-drain output port; the pin
circuits can withstand loads up to 9 volts.
8
58–51
—
ADC0–ADC7
I
Analog input pins for A/D converter module.
Alternatively used as general-purpose
digital input port 7.
41, 43–44,
46–50
P7.0–P7.7
AVREF, AVSS
—
A/D converter reference voltage and
ground
—
42, 45
—
RxD
I/O
Serial data RxD pin for receive input and
transmit output (mode 0)
6
20
—
TxD
O
Serial data TxD pin for transmit output and
shift clock input (mode 0)
7
21
—
PWM0,
PWM1
O
Pulse width modulation output pins
7
23, 22
—
TA, TB
O
Output pins for timer A and timer B
5
13, 12
P2.6, P2.7
INT0–INT11
I
External interrupt input pins
4
24–27,
33–40
P3.0–P3.3,
P4.0–P4.7
TCCK, TDCK
I
External clock input for timer C and timer D
4
24, 25
P3.0, P3.1
TCG, TDG
I
Gate input pins for timer C and timer D
4
26, 27
P3.2, P3.3
CAP
I
Capture data input for PWM module
4
30
P3.6
WAIT
I
Input pin for the slow memory timing signal
from the external interface
4
31
P3.7
RESET
I
System reset pin (pull-up resistor: 220 k
)
1
64
—
EA
I
External access (EA) pin with two modes:
5 V input: normal ROM-less operation with
external interface (0 V is not allowed)
9 V–10 V input: for factory test mode
—
65
—
VDD1, VSS1
—
Power input pins for CPU operation
(internal)
—
74, 61
—
VDD2, VSS2
—
Power input pins for port output (external)
—
11, 32
—
XIN, XOUT
—
Main oscillator pins
—
59, 60
—
AS
O
Address strobe
7
62
—
NC
—
No connection pins (connect to VSS)
—
62, 63
—
NOTE
VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also.
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