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參數(shù)資料
| 型號(hào)： | S3C70F4XX-AV |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP30 |
| 封裝： | 0.400 INCH, SDIP-30 |
| 文件頁(yè)數(shù)： | 179/179頁(yè) |
| 文件大小： | 1070K |
| 代理商： | S3C70F4XX-AV |
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INTERRUPTS
S3C70F2/C70F4/P70F4
7-12
INTERRUPT FLAGS
There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in-
terrupt, the interrupt master enable flag, which enables or disables all interrupt processing.
Interrupt Master Enable Flag (IME)
The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an
IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the
IME flag is set to logic one.
The IME flag is located in the IPR register (IPR.3), and is mapped to bit address FB2H.3. It can be directly be
manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB).
Interrupt Enable Flags (IEx)
IEx flags, when set to logic one, enable specific interrupt requests to be served. When the interrupt request flag
is set to logic one, an interrupt will not be served until its corresponding IEx flag is also enabled.
Interrupt enable flags are mapped to the RAM address area FB8H–FBFH, and can be read, written, or tested
directly by 1-bit instructions (BITS and BITR). IEx flags can be addressed directly at their specific RAM
addresses, despite the current value of the enable memory bank (EMB) flag.
Interrupt Request Flags (IRQx)
Interrupt request flags, located in the RAM area FB8H-FBFH, are read/write addressable by 1-bit or 4-bit in-
structions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value
of the enable memory bank (EMB) flag.
When a specific IRQx lag is set to logic one, the corresponding interrupt request is generated. The flag is then
automatically cleared to logic zero by hardware when the interrupt has been served. Exceptions are the watch
timer interrupt request flag, IRQW, and key interrupt request flag IRQK, which must be cleared by software after
the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software.
In summary, follow these guidelines for using IRQx flags:
1.
IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.
2.
IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been served (with the
exception of IRQW and IRQK).
3.
When IRQx is set to "1" by software, an interrupt is generated.
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