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參數資料
| 型號： | S29WS128N0LBFI011 |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| 中文描述： | 256/128/64兆位的CMOS 1.8伏只有同時讀/寫突發(fā)模式閃存 |
| 文件頁數： | 15/99頁 |
| 文件大小： | 1091K |
| 代理商： | S29WS128N0LBFI011 |
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20
S29WS-N_00_G0 January 25, 2005
Adva nce
Information
7
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
does not occupy any addressable memory location; rather, it is composed of latches that store
the commands, along with the address and data information needed to execute the command.
The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing
them in an improper sequence may place the device in an unknown state, in which case the sys-
tem must write the reset command to return the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state
of each control pin for any particular operation.
Table 7.1. Device Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
7.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware re-
set. Asynchronous read requires that the CLK signal remain at VIL during the entire memory read
operation. To read data from the memory array, the system must first assert a valid address on
Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD#
latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH.
Operation
CE#
OE#
WE#
Addresses
DQ15–0
RESET#
CLK
AVD#
Asynchronous Read - Addresses Latched
L
H
Addr In
Data Out
H
X
Asynchronous Read - Addresses Steady State
L
H
Addr In
Data Out
H
X
L
Asynchronous Write
L
H
L
Addr In
I/O
H
X
L
Synchronous Write
L
H
L
Addr In
I/O
H
Standby (CE#)
H
X
HIGH Z
H
X
Hardware Reset
X
HIGH Z
L
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
X
H
Addr In
X
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
LL
H
X
Burst
Data Out
HH
Terminate current Burst read cycle
H
X
H
X
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
H
X
HIGH Z
L
X
Terminate current Burst read cycle and start new
Burst read cycle
LX
H
Addr In
I/O
H
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| S29WS128N0LBFI012 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
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| S29WS128N0LBFI112 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
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