參數(shù)資料
型號(hào)： S29NS512P
廠商： Spansion Inc.
英文描述： MirrorBit Flash Family
中文描述： MirrorBit閃存系列
文件頁(yè)數(shù)： 28/86頁(yè)
文件大?。?/td> 2234K
代理商： S29NS512P
28
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
6.3
Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
When the device first powers up, it is enabled for Asynchronous read and can be automatically enabled for
burst mode and the address is latched on the first rising edge of CLK input, while AVD# is held low for one
clock cycle.
Prior to activating the clock signal, the system should determine how many wait states are desired for the
initial word (t
IACC
) of each burst access, what mode of burst operation is desired and how the RDY signal
transitions with valid data. The system would then write the configuration register command sequence.
At startup the system writes the
Set Configuration Register
command sequence to optimize the system
performance.
The data is output t
IACC
after the
rising edge
of the first CLK. Subsequent words are output t
BACC
after the
rising edge of each successive clock cycle, which automatically increments the internal address counter.
Note that data is output only at the rising edge of the clock. RDY indicates the initial latency.
Note that the device has a fixed internal address boundary that occurs every 128 words. No boundary
crossing latency is required when the device operates with wait states set from 2 to 9.
6.3.1
Latency Tables for Variable Wait State
Tables 6.2
–
6.9
show the latency for variable wait state in a normal Burst operation.
Table 6.2
Address Latency for 9 Wait States
Word
Initial Wait
0
9 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
1 ws
D8
2
D2
D3
D4
D5
D6
D7
1 ws
1 ws
D8
3
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
D8
4
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D8
5
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
D8
6
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D8
7
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D8
Table 6.3
Address Latency for 8 Wait States
Word
Initial Wait
0
8 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
1 ws
D8
D9
3
D3
D4
D5
D6
D7
1 ws
1 ws
D8
D9
4
D4
D5
D6
D7
1 ws
1 ws
1 ws
D8
D9
5
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D8
D9
6
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
D8
D9
7
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D8
D9
相關(guān)PDF資料
PDF描述
S29NS512P0PBJW000 MirrorBit Flash Family
S29NS512P0PBJW003 MirrorBit Flash Family
S29NS512P0SBJW000 MirrorBit Flash Family
S29NS512P0SBJW003 MirrorBit Flash Family
S29NS512PABBJW000 MirrorBit Flash Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS512P0PBJW000 功能描述:閃存 512M (32MX16) 66MHz Simultaneous R/W RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29NS512P0PBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS512P0SBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS512P0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
S29NS512PABBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family
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