參數(shù)資料
型號： S29NS512P0SBJW000
廠商： SPANSION LLC
元件分類： DRAM
英文描述： MirrorBit Flash Family
中文描述： 32M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 8 X 9.20 MM, LEAD FREE, TFBGA-64
文件頁數(shù)： 74/86頁
文件大?。?/td> 2234K
代理商： S29NS512P0SBJW000
74
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 10.17
Synchronous Data Polling Timings/Toggle Bit Timings
Notes
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle
bits stop toggling.
3. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle
before data.
Figure 10.18
DQ2 vs. DQ6
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 10.19
Latency with Boundary Crossing
Notes
1. RDY active with data (CR0.8 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (CR0.8 = 1 in the Configuration Register).
3. Figure shows the device not crossing a bank in the process of performing an erase or program.
CE#
CLK
AVD#
OE#
RDY
Status Data
Status Data
V A
V A
t
IACC
t
IACC
A/DQ15–
A/DQ0
Amax–
A16
V A
V A
Enter
Erase
Erase
Resume
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
Suspend
Program
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Embedded
Erasing
CLK
Address
(hex)
D124
D125
D126
D127
D128
D129
D130
(stays high)
AVD#
RDY
(Note 1)
Data
CE#(stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C
7D
7E
7F
7F
80
81
82
83
latency
RDY
(Note 2)
latency
t
RACC
t
RACC
t
RACC
t
RACC
Invalid
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