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參數(shù)資料
| 型號： | S29NS128P0PBJW003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA64 |
| 封裝： | 6.20 X 7.70 MM , LEAD FREE, TFBGA-64 |
| 文件頁數(shù)： | 42/86頁 |
| 文件大?。?/td> | 2234K |
| 代理商： | S29NS128P0PBJW003 |
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42
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
Software Functions and Sample Code
The following is a C source code example of using the chip erase function. Refer to the
Spansion Low Level
Driver User’s Guide
(
www.spansion.com
m) for general information on Spansion Flash memory software
development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
*/
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
/* write chip erase command
*/
*/
*/
*/
6.5.5
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device immediately
terminates the time-out period and suspends the erase operation. The Erase Suspend command allows the
system to interrupt a sector erase operation and then read data from, or program data to, any sector not
selected for erasure. The bank address is required when writing this command. This command is valid only
during the sector erase operation, including the minimum t
SEA
time-out period during the sector erase
command sequence. The Erase Suspend command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the t
SEA
time-out period has expired and during the sector
erase operation, the device requires a maximum of t
ESL
(erase suspend latency) to suspend the erase
operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system
can read data from or program data to any sector not selected for erasure. (The device
erase suspends
all
sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status
information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to
Table 6.27
for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode.
The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to the
Write Buffer Programming
section and the
Autoselect
section for details.
To resume the sector erase operation, the system must write the Erase Resume command. The bank
address of the erase-suspended bank is required when writing this command. Further writes of the Resume
command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Note:
While an erase operation can be suspended and resumed multiple times, a minimum delay of t
ERS
(Erase Resume to Suspend) is required from resume to the next suspend.
Table 6.18
Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
2
Unlock
Write
Base + 554h
Base + 2AAh
0055h
3
Setup Command
Write
Base + AAAh
Base + 555h
0080h
4
Unlock
Write
Base + AAAh
Base + 555h
00AAh
5
Unlock
Write
Base + 554h
Base + 2AAh
0055h
6
Chip Erase Command
Write
Base + AAAh
Base + 555h
0010h
相關PDF資料 |
PDF描述 |
|---|---|
| S29NS128P0SBJW000 | MirrorBit Flash Family |
| S29NS128P0SBJW003 | MirrorBit Flash Family |
| S29NS128PABBJW000 | MirrorBit Flash Family |
| S29NS128PABBJW003 | MirrorBit Flash Family |
| S29NS256P | MirrorBit Flash Family |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS128P0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128P0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128PABBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128PABBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS256N | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
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