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參數(shù)資料
| 型號： | S29NS128P0PBJW000 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA64 |
| 封裝： | 6.20 X 7.70 MM , LEAD FREE, TFBGA-64 |
| 文件頁數(shù)： | 31/86頁 |
| 文件大?。?/td> | 2234K |
| 代理商： | S29NS128P0PBJW000 |
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February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
31
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 6.1
Synchronous Read Flow Chart
6.3.2
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting address given
and then wraps around to address 000000h when it reaches the highest addressable memory location. The
burst read mode continues until the system drives CE# high, or RESET= V
IL
. Continuous burst mode can
also be aborted by asserting AVD# low and providing a new address to the device.
If the address being read crosses a 128-word line boundary within the same bank, but not into a program or
erase suspended sector, as mentioned above, additional latency cycles are required as reflected by the
configuration register table (
Table 6.11
) and
Tables 6.2
–
6.9
.
If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device
provides read status information and the clock is ignored. Upon completion of status read or program or erase
operation, the host can restart a burst read operation using a new address and AVD# pulse.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Set Configuration Registers
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR0-CR1
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
Read Next Data
RD = DQ[15:0]
Wait t
IACC
+
Programmable Wait State Setting
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
End of Data
Yes
Crossing
Boundary
No
Yes
Completed
Delay X Clocks
Unlock Cycle 1
Unlock Cycle 2
RA = Read Address
RD = Read Data
Command Cycle
CR = Configuration Registers
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
Note: Setup Configuration Register parameters
Refer to the Latency tables.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS128P0PBJW003 | MirrorBit Flash Family |
| S29NS128P0SBJW000 | MirrorBit Flash Family |
| S29NS128P0SBJW003 | MirrorBit Flash Family |
| S29NS128PABBJW000 | MirrorBit Flash Family |
| S29NS128PABBJW003 | MirrorBit Flash Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS128P0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128P0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128P0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128PABBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128PABBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
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