參數(shù)資料
型號(hào)： S29GL128M90FAIR20
廠商： SPANSION LLC
元件分類： DRAM
英文描述： MOSFET, Switching; VDSS (V): -30; ID (A): -14; Pch : 2.5; RDS (ON) typ. (ohm) @10V: 0.009; RDS (ON) typ. (ohm) @4V[4.5V]: [0.015]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 3500; toff (µs) typ: 0.31; Package: SOP-8
中文描述： 8M X 16 FLASH 3V PROM, 90 ns, PBGA64
封裝： 13 X 11 MM, FORTIFIED, BGA-64
文件頁數(shù)： 104/160頁
文件大?。?/td> 2142K
代理商： S29GL128M90FAIR20
104
S29GLxxxM MirrorBit
TM
Flash Family
S29GLxxxM_00A5 April 30, 2004
P r e l i m i n a r y
reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without in-
tervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of in-
dividual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to
be programmed. The effective word programming time using write buffer pro-
gramming is approximately four times shorter than the single word programming
time.
Any bit in a word cannot be programmed from “0” back to a “1.”
Attempt-
ing to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status
bits to indicate the operation was successful. However, a succeeding read will
show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass mode command
sequence is all that is required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time. Tables 31 and 32 show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h. The second cycle must contain the data 00h. The de-
vice then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming will occur. The fourth cycle writes the sec-
tor address and the number of word locations, minus one, to be programmed. For
example, if the system will program 6 unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits A
MAX
–A
4
. All subsequent address/
相關(guān)PDF資料
PDF描述
S29GL128M90FAIR22 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
S29GL128M90FAIR23 MOSFET, Switching; VDSS (V): -60; ID (A): -5; Pch : 2.0/3.0; RDS (ON) typ. (ohm) @10V: 0.06; RDS (ON) typ. (ohm) @4V[4.5V]: [0.09]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 1350; toff (µs) typ: 0.055; Package: SOP-8
S29GL128M90FAIR80 MOSFET, Switching; VDSS (V): -60; ID (A): -5; Pch : 2.0/3.0; RDS (ON) typ. (ohm) @10V: 0.06; RDS (ON) typ. (ohm) @4V[4.5V]: [0.09]; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 1350; toff (µs) typ: 0.055; Package: SOP-8
S29GL128M90FAIR82 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
S29GL128M90FAIR83 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29GL128M90TAIR10 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 90ns 56-Pin TSOP Tray
S29GL128M90TAIR13 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 16MX8/8MX16 90NS 56TSOP - Tape and Reel
S29GL128M90TFIR10 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 16M x 8/8M x 16 90ns 56-Pin TSOP Tray
S29GL128N10FFI010 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 128Mbit 16M/8M x 8bit/16bit 100ns 64-Pin Fortified BGA Tray 制造商:Spansion 功能描述:MIRRORBIT FLASH 128MB SMD 29LV128
S29GL128N10FFI020 制造商:Spansion 功能描述:Flash - NOR IC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*