- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385802 > S29GL064M90FFIR02 (Spansion Inc.) 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology PDF資料下載
參數(shù)資料
| 型號(hào)： | S29GL064M90FFIR02 |
| 廠商： | Spansion Inc. |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| 中文描述： | 3.0伏只頁面模式閃存具有0.23微米工藝技術(shù)的MirrorBit |
| 文件頁數(shù)： | 110/160頁 |
| 文件大?。?/td> | 2142K |
| 代理商： | S29GL064M90FFIR02 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁當(dāng)前第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁
110
S29GLxxxM MirrorBit
TM
Flash Family
S29GLxxxM_00A5 April 30, 2004
P r e l i m i n a r y
Any commands written during the chip erase operation are ignored. However,
note that a
hardware reset
immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
31
and Table
32
shows
the address and data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 μs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 μs, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written.
Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode.
Note that the SecSi Sector, au-
toselect, and CFI functions are unavailable when an erase operation is in
progress
.
The system must rewrite the command sequence and any additional
addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a
hardware reset
im-
mediately
terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29GL064M90FFIR03 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL064M90FFIR10 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL064M90FFIR12 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL064M90FFIR13 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
| S29GL064M90FFIR20 | 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL064M90FFIR2 | 制造商:Spansion 功能描述: |
| S29GL064M90TAIR00 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8 90ns 48-Pin TSOP Tray |
| S29GL064M90TAIR2 | 制造商:Spansion 功能描述: |
| S29GL064M90TAIR20 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 90ns 56-Pin TSOP Tray |
| S29GL064M90TAIR3 | 制造商:Spansion 功能描述:NOR Flash, 4M x 16, 48 Pin, Plastic, TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。