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參數(shù)資料
| 型號(hào)： | S29GL032M10TFCR32 |
| 廠商： | Spansion Inc. |
| 英文描述： | High Temperature Tantalum Capacitor Kit |
| 中文描述： | MirrorBit閃存系列 |
| 文件頁(yè)數(shù)： | 23/159頁(yè) |
| 文件大?。?/td> | 5216K |
| 代理商： | S29GL032M10TFCR32 |
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Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
119
Da tash eet
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is,
the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that are selected for erasure. (The system
may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 37 on page 120 to compare outputs for DQ2 and DQ6.
Figure 8, on page 118 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” ex-
plains the algorithm. See also the “RY/BY#: Ready/Busy#” on page 116 subsection. Figure 20, on page 134
shows the toggle bit timing diagram. Figure 21, on page 134 shows the differences between DQ2 and DQ6 in
graphical form.
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then de-
termine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went
high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation.
If it is still toggling, the device did not completed the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 did not go
high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining
the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the algorithm when it returns to determine the status of the
operation (top of Figure 6, on page 111).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device to the reading the array (or to
erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure
started. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the
system can be assumed to be less than 50 s, the system need not monitor DQ3. See the “Sector Erase Command
Sequence” on page 110 section.
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