參數(shù)資料
型號： S29GL032M10TCCR52
廠商： Spansion Inc.
英文描述： MirrorBit Flash Family
中文描述： MirrorBit閃存系列
文件頁數(shù)： 158/159頁
文件大?。?/td> 5216K
代理商： S29GL032M10TCCR52
98
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
Data s he et
Factory Locked: SecSi Sector Programmed and Protected At the Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sec-
tor cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses
000000h–000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion programming service
(Customer Factory Locked). The devices are then shipped from the factory with the SecSi Sector permanently
locked. Contact your sales representative for details on using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group without using
VID. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last
sector group independently of whether those sector groups were protected or unprotected. Note that if WP#/ACC
is at VIL when the device is in the standby mode, the maximum input load current is increased. See Table 22 on
Note: If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was
previously set to be protected or unprotected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 35 on page 113 and Table 36 on page 114 for command definitions). In
addition, the following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or
from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal program/erase circuits are disabled, and the device re-
sets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide
the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge
of WE#. The internal state machine is automatically reset to the read mode on power-up.
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