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  • 參數(shù)資料
    型號: S29GL032M10BCIR12
    廠商: Spansion Inc.
    英文描述: Conductive Polymer Chip Capacitors / T520 Series - High Temperature; Capacitance [nom]: 330uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Conductive Polymer; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-31; Termination: Solder Coated (SnPb, Pb 5% min); Body Dimensions: 7.3mm x 4.3mm x 2.8mm; Temperature Range: -55C to +125C; Container: Tape &amp; Reel; Qty per Container: 500; Features: Low Temperature
    中文描述: MirrorBit閃存系列
    文件頁數(shù): 85/159頁
    文件大?。?/td> 5216K
    代理商: S29GL032M10BCIR12
    Octorber 18, 2004 S29GLxxxM_00_B3
    S29GLxxxM MirrorBitTM Flash Family
    31
    Da tash eet
    Accelerated Program Operation
    The device offers accelerated program operations through the ACC function. This is one of two functions provided
    by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to allow faster man-
    ufacturing throughput at the factory.
    If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode,
    temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time
    required for program operations. The system would use a two-cycle program command sequence as required by
    the Unlock Bypass mode. Removing VHH from the WP#/ACC or ACC pin, depending on model number, returns the
    device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations other than ac-
    celerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is
    at VIH.
    Autoselect Functions
    If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can
    then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0.
    Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” on page 79 and “Autoselect Com-
    mand Sequence” on page 104 sections for more information.
    Standby Mode
    When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode,
    current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of
    the OE# input.
    The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note
    that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ±
    0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access
    time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.
    If the device is deselected during erasure or programming, the device draws active current until the operation is
    completed.
    Refer to “DC Characteristics” on page 122 for the standby current specification.
    Automatic Sleep Mode
    The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this
    mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#,
    and OE# control signals. Standard address access timings provide new data when addresses are changed. While
    in sleep mode, output data is latched and always available to the system. Refer to “DC Characteristics” on
    page 122 for the automatic sleep mode current specification.
    RESET#: Hardware Reset Pin
    The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin
    is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all
    output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets
    the internal state machine to reading array data. The operation that was interrupted should be reinitiated once
    the device is ready to accept another command sequence, to ensure data integrity.
    Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws
    CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.
    The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,
    enabling the system to read the boot-up firmware from the Flash memory.
    Refer to “AC Characteristics” on page 124 for RESET# parameters and to Figure 15, on page 127 for the timing
    diagram.
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