
September 10, 2007 S29GL-A_00_A11
S29GL-A
81
D a t a
S h e e t
Figure 16.9
Toggle Bit Timings (During Embedded Algorithms)
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 16.10
DQ2 vs. DQ6
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
OE#
CE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read)
(second read)
(stops toggling)
t
CEPH
t
AHT
t
AS
DQ6 / DQ2
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Enter
Erase
Erase
Resume
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
Suspend
Program
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Embedded
Erasing